Z80 8-Bit Microprocessor IP Core (FPGA and ASIC)

Z80 IP Core General Description:

The D Z80 is an advanced 8-bit microprocessor with 208 bits of user accessible registers, composed of six general purpose registers, able to be used individually as either 8-bit registers, or as 16-bit register pairs. In addition to these registers, the DZ80 supports two sets of accumulator and flag registers. The DZ80 contains Stack Pointer, Program Counter, two Index Registers, a REFRESH Register, and an INTERRUPT register. All output signals are fully decoded and timed to control standard memory or peripheral circuits.

The DZ80 is supported by a wide range of peripherals.

DZ80 is fully customizable and delivered in the exact configuration to meet users requirements. There is no need to pay extra for not used features and silicon.
The core includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

Units

Control Unit
Performs the core synchronization and data flow control. This module manages execution of all instructions. The Control Unit also manages execution of HALT state and waking-up the processor from the HALT mode.

Instruction Decoder
Performs an instruction opcode decoding and the control functions for all other blocks.

Interrupt Controller
Interrupt Controller manages execution of maskable and nonmaskable interrupts. It contains a Interrupt Enable register. Interrupt controller is responsible for the special M1 Cycle generation and wait states implementation during interrupt service.

Bus Controller
Data Memory & SFR’s (Special Function Register) interface controls access into the program and data memories and special registers. It contains Program Counter (PC), Stack Pointer (SP) register, Index registers and related logic.

ALU
Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. Contains accumulator CPU registers and related logic such as arithmetic and logic unit. ALU communicates with internal registers and the external data bus by using internal data bus.

Licensing Options:

Single Site license option is provided to companies designing in a single site.

Multi Sites license option is provided to companies designing in multiple sites.

Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.

Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

Price:

www.HiTechGlobal.com

HiTech Global Design & Distribution, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124
Tel:+ 1 408 781-8043
Fax: + 1 408 268-4173
Email: info@hitechglobal.com