SPDIF-AES/EBU to I2S Converter IP Core

Overview:

The CWda03 is a digital audio receiver IP core implementing the SPDIF, AES/EBU, AES3 or IEC60958 standards. The CWda03 inputs an SPDIF signal and samples it with a fast clock to extract the clock, audio and control data from it. It outputs PCM audio data in the well known I2S format, popular in many data converters.

Functional Description:

Glitch Filter & Digital Data and Clock Recovery:
filters glitches due to slow transitions in the SPDIF-AES/EBU signal; clock and data recovery based on fast sampling and edge detection.

SPDIF-AES/EBU Decoder: decodes the SPDIF-AES/EBU signal according to the IEC60958, AES3 or AES/EBU standards.

I2S Output FIFO: converts LSB-first serial data to the MSB-first I2S format. When mode=0, an external PLL circuit must be used to filter the jitter out of the recovered clock. The jitter-free clock is used to retrieve the data signal from a shallow output FIFO. When mode=1, the PLL circuit is not necessary, but the output data contains jitter.

Key Features:

Supports the following standards: IEC60598 (SPDIF), AES3, AES/EBU
Uses a fixed clock frequency, unrelated to the sample frequency
Supports sample rates up to frequency fclk/512 (192KHz for fclk ≥ 98MHz)
Supports up to 24 bits per sample
Extracts the control bits from the incoming bitstream
Reports input sample rate
Lock time less than 3 frames
Purely digital receiver
Two modes of operation: with or without external PLL (jitter attenuation of the output clock preformed in the first mode only)
Low power mode when idle

Benefits:
Completely digital receiver. No need to use input PLL for synchronization.

Applications: 
Digital audio (CD, SACD, DVD-Audio), or multimedia systems. (VCD, SVCD, DVD, etc.).

Deliverables:

  • Detailed datasheet and user documentation for system integration.
  • HDL testbench covering all functionalities of the core and including automatic verification of the correctness of the responses.
  • Options:
    o FPGA Netlist
    o HDL (VHDL or VERILOG) source code.
    o Simulation script.
    o Synthesis and/or place and route scripts.
    o Prototyping boards.

Part Number: CWda03

Price: Quote Me

How To Purchase:

 

  Implementation Results:
 

Family

 Example Device  

Fmax (MHz)  

Slices  

IOB

 GCLK  

 BRAM  

Design Tools  

 Spartan-IIE

 XC2S50E-6  

87

234

26

1

0

ISE 6.3.03i

 Spartan-3  

 XC3S50-4  

129

231

27

1

0

ISE 6.3.03i

 Virtex-II Pro  

 XC2VP2-5  

165

228

27

1

0

ISE 6.3.03i

 Virtex-II

 XC2V40-4  

153

230

27

1

0

ISE 6.3.03i

 Virtex-4  

 XC4Vfx12-10  

180

230

27

1

0

ISE 6.3.03i

Mode = 0 Mode = 1
Technology Resources Frequency (fClk) Resources Frequency (fClk)
UMC 180 nm 3,990 Gates 950 MHz 3,450 Gates 900 MHz

Other Digital Audio IP Cores:

IP Name/Part #

Description

CWda03 SPDIF-AES/EBU to I2S Converter                  
CWda04 I2S to SPDIF-AES/EBU Converter                  
SPDIF-CWda14 Configurable SPDIF-AES/EBU Receiver
SPDIF-CWda15 Configurable SPDIF-AES/EBU Transmitter
I2S-CWda16 Configurable Digital Audio Serial Input
I2S-CWda17 Configurable Digital Audio Serial Output
SDI-CWda41 SDI Audio De-embedder
SDI-CWda42 SDI Audio Embedder
CWda30 3rd Order Stereo Digital Audio Sigma-Delta Modulator                   
SRC-CWda50 Stereo / Mono Sample Rate Converter
SRC-CWda52 Multi-Channel Audio Sample Rate Converter (ASRC)



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