I2S Receiver, Digital Audio IP Cores

I2S Receiver IP Core

Overview:

Converts a serial I2S bitstream into a parallel audio stream in the Coreworks Audio Parallel Interface (CWAPI) used in many of our cores. Uses an asynchronous double clock domain FIFO with an input clock signal mclk=256 Fs and an output clock signal fclk unrelated to the sample rate.

Functional description:

I2S Input: this input stage converts a serial I2S bitstream into a parallel audio stream in the Coreworks Audio Parallel Interface (CWAPI) used in many of our cores.

Synchronization FIFO: asynchronous double clock domain FIFO. Receives audio samples in parallel from the I2S input stage using a clock signal mclk=256 Fs, and outputs the audio samples in CWAPI format to a user core using a clock signal fclk unrelated to the sample rate.

Key Features:

• Compliant with the I2S standard.
• Flexible Coreworks Audio Parallel Interface (CWAPI) at the output, which permits bridging to other standard interfaces (SPDIF-AES/EBU, IBM CoreConnect™, AMBA™,etc).
• Double clock domain design: FCLK, a fast system clock unrelated to the sample rate; MCLK, a master clock frequency of value 256*Fs.
• Configurable FIFO depth and width.
• Supports any sample rate, which is defined by MCLK (384kHz for mclk = 98 MHz).
• Supports up to 24 bits per sample.
• Low power mode when idle.

Benefits:

Easily creates an I2S signal if you are using Coreworks receiver IPs, sample rate converters (to be available soon), etc.

Deliverables:

Detailed datasheet and user documentation for system integration.
HDL Testbench covering all functionalities of the core and including automatic verification of the correctness of the responses.
Options:
o FPGA Netlist
o HDL (VHDL or Verilog) source code.
o Simulation script.
o Synthesis and/or place and route scripts.
o Prototyping boards.

Part Number: CWda10

Price:

How To Purchase

Implementation Results:

Family	Example Device	Fmax (MHz)	Slices	IOB	GCLK	BRAM	Design Tools
Spartan-3	XC3S50-4	145	39	36	3	1	ISE 6.3.02i
Spartan-IIE	XC2S50E-6	130	44	36	3	2	ISE 6.3.02i
Virtex-II Pro	XC2VP2-5	197	39	36	3	1	ISE 6.3.02i
Virtex-II	XC2V40-4	162	39	36	3	1	ISE 6.3.02i
Virtex-4	XC4Vfx12-10	186	39	36	3	1	ISE 6.3.02i

Other Digital Audio IP Cores:

IP Name/Part #	Description
CWda01	SPDIF-AES/EBU Feed-Forward Receiver
CWda02	SPDIF-AES/EBU Feed-Forward Transmitter
CWda03	SPDIF-AES/EBU to I2S Converter
CWda04	I2S to SPDIF-AES/EBU Converter
CWda05	SPDIF-AES/EBU Transmitter
CWda06	I2S Transmitter
CWda07	SPDIF-AES/EBU Self-Clocked Receiver
CWda10	I2S Receiver
CWda12	SPDIF to non-PCM Encoded Audio
CWda13	Non-PCM Encoded Audio to SPDIF
CWda14	Configurable SPDIF-AES/EBU Receiver
CWda17	Configurable Digital Audio Serial Output
CWda20	CoreConnect ^TM Audio Input
CWda21	CoreConnect ^TM Audio Output
CWda30	3rd Order Stereo Digital Audio Sigma-Delta Modulator
CWda50	Stereo / Mono Sample Rate Converter
CWda52	Multi-Channel Audio Sample Rate Converter (ASRC)

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