USB 2.0 Device IP Core

USB 2.0 Device Only IP Core (Certified)

A certified USB 2.0 Device IP Core that provides high performance small footprint solution for quick and easy implementation of a USB Device interface.

Main Features:
The USB 2.0 Device IP Core is fully USB 2.0 compliant. The main features of the USB 2.0 Device IP Core are:

USB 2.0 high performance operation
ULPI L2+ Interface, ULPI wrapper and FS only transceiver interface available
Full USB peripheral support
High Speed and Full Speed mode support
Up to 16 endpoints
Bulk, interrupt and isochronous transfers
Slave and Master System Interface:
WISHBONE, CoreConnect, AMBA, and AVALON
Customer specified bus interface
No dedicated local memory required
Compact and cost-effective solution for SoC

An USB 2.0 Device IP Core is ideal for applications where the target device must act as a peripheral only. It provides portable devices with a cost-effective way of conducting point-to-point communications using the USB bus.

Architecture:
The USB 2.0 Device IP Core supports both High Speed and Full Speed operations. It will automatically perform the required negotiation to determine if it's counter part supports High Speed and fall back to Full Speed operation if it does not. The speed negotiation is supported in device and host modes.

UTM + L2PHY Interface
The USB 2.0 Device IP Core features an industry standard UTMI+ L2 interface. Any of-the-shelf UTMIL+ L2 compliant PHY or PHY IP can be used with this IP Core.

ULPI Interface
An optional ULPI interface is provided for interface to a ULPI compliant PHY.

MCU Interfaces
The USB 2.0 Device IP Core features two WISHBONE interfaces: The Slave Interface is used to access all core internal registers. The Master Interface allows the USB 2.0 Device IP Core to share the system memory for buffering data. It is also used to store Transfer Descriptors when operating in Host Mode.

Buffer Memory
The USB 2.0 Device IP Core does not need dedicated buffer memory. It's WISHONE Master Interface and the internal DMA engine allow it to share the SoC's main memory for its buffers. Optionally we can also provide a WISHBONE bridge to attach standard dedicated SRAM.

Verification:
The USB 2.0 Device IP Core comes with an elaborate test bench that demonstrates the usage and programming of the USB 2.0 Device IP Core.

Size & Speed:
Sample Synthesis results for an implementation with 4 endpoints

Description	Gate Count	Operating Frequency
UMC 0.18u	TBD	60MHz PHY, TBD MHz SOC
Xilinx Virtex 2 1000-4	1,907 Slices	60MHz PHY, 160 MHz SOC
Altera Stratix 3 (XC3S1000-5)	1,889 Slices	60MHz PHY, 150 MHz SOC

These synthesis results are provided for reference only. Please contact us for estimates for your application

Price:

How To Purchase

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