USB 2.0 On-The-Go (OTG) IP Core (FS and HS)- Certified

A ‘Dual-Role’ USB 2.0 On-The-Go  (OTG) IP Core that operates as both an USB 2.0 Peripheral or as an USB 2.0 OTG Host in a point-to-point communications with another USB device. 


Main Features: 
The USB 2.0 OTG IP Core is fully USB 2.0 and USB 2.0 On-The-Go Supplement compliant. The main features of the USB OTG IP Core are:

  • True Dual-Role capability

  • OTG high performance host mode

  • ULPI L2+ Interface, ULPI wrapper and FS only transceiver interface available

  • Full USB peripheral support

  • Session request protocol support

  • Host negotiation protocol support

  • High Speed and Full Speed mode support

  • Up to 16 endpoints

  • Bulk, interrupt and isochronous transfers

  • Slave and Master System Interface:
              - WISHBONE, CoreConnect, AMBA, AVALON, Customer specified bus interface

  • No dedicated local memory required
    Compact and cost-effective solution for SoC

An USB OTG IP Core is ideal for applications where the target device must act as a peripheral and as a host, depending the situation. It provides portable devices with a cost-effective way of conducting point-to-point communications using the USB bus. A good example is a PDA which has to be a peripheral that can sync with a host PC, but can also be a host when a peripheral, such as a keyboard or a camera, is connected to it.

The USB 2.0 OTG IP Core supports both High Speed and Full Speed operations. It will automatically perform the required negotiation to determine if it's counter part supports High Speed and fall back to Full Speed operation if it does not. The speed negotiation is supported in device and host modes.

UTM + L2PHY Interface 
The USB 2.0 OTG IP Core features an industry standard UTMI+ L2 interface. Any of-the-shelf UTMIL+ L2 compliant PHY or PHY IP can be used with this IP Core. 

MCU Interfaces 
The USB 2.0 OTG IP Core features two WISHBONE interfaces, which can be easily adapted to AMBA AHB bus interface with our WISHBONE/AMBA bridge. The Slave Interface is used to access all core internal registers. The Master Interface allows the USB 2.0 OTG IP Core to share the system memory for buffering data. It is also used to store Transfer Descriptors when operating in Host Mode. 

Buffer Memory 
The USB 2.0 OTG IP Core does not need dedicated buffer memory. It's WISHONE Master Interface and the internal DMA engine allow it to share the SoC's main memory for its buffers. Optionally we can also provide a WISHBONE bridge to attach standard dedicated SRAM. 

The Host Controller block is active when the USB OTG IP core operates in a OTG host mode. In this mode it can control USB peripherals that are attached to it. It provides full support for session request and host negotiation protocols.

The USB 2.0 OTG IP Core comes with an elaborate test bench that demonstrates the usage and programming of the USB 2.0 OTG IP Core. 

Size & Speed:
Sample Synthesis results for an 0.18u process. The goal was smallest and fastest implementation. 

Description Gate Count Operating Frequency
UMC 0.18u

40K Gates




 Example Device  

 Fmax3 (MHz)  







 Design Tools  










 ISE 6.2.03i  










 ISE 6.2.03i  

 Virtex-II Pro









 ISE 6.2.03i  










 ISE 6.2.03i  

Price: Quote Me

How To Purchase  

Evaluation Daughter Card:

A P160 based daughter card with SD and USB 2.0  is available for evaluation of SDIO and USB 2.0 Core.

Part Number: HTG-V4P-USB


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HiTech Global, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124
Tel:+ 1 408 781-7778
+ 1 408 268-4173