HTG-616: Xilinx Virtex™ -6 HXT 16-lane PCI Express Optical Network Card
Powered by Xilinx Virtex-6 HX380T or HX565T FPGA, this optical network card provides access to sixteen lanes of PCI Express Gen 2 (64 Gbps raw data throughput), two SFP+ & two QSFP+ optical connectors (100 Gbps), up to 16 GB of DDR3 SO-DIMM, QDR II, ten 11.18 Gbps and ten 6.6Gbps serial ports. The on-board FPGA Mezzanine Connectors (FMC) along with off-the-shelf FMC modules, expend the functionality of the board for variety of different applications.
One QSFP+ port is powered by two external PHY chips (with Electrical Dispersion Compensation) supporting short range, medium range, and long range optical interfaces. The second QSFP+ port along with two additional single SFP+ ports are connected directly to the GTH serial transceivers of the on-board FPGA (also tested by Xilinx 40Gig Ethernet MAC/PCS IP core)
Extensible FPGA Framework (EFW) provides a verified set of productivity solutions, including module targeted physical interface components, device drivers and APIs for the HTG-616 platform. The EFW enables end user to skip the tedious and time consuming phase of the platform's bring-up by providing targeted and hardware verified physical interfaces.
Additionally, the framework allows users to simulate, integrate and test Ethernet and DMA cores (licensed separately) in their designs with time limited synthesizable binaries and simulation libraries.
Following figure shows the elements and interfaces of the framework.
The base framework provides all the design files, device drivers and API to access the memory mapped registers inside the FPGA. It enables an end user to instantiate and control custom logic blocks through the GUI application.
Another key feature of the base EFW is the capability to program and erase the G18 BPI memory on the HTG-616 through the PCIe interface at very high speeds. Integrating the field upgradeable controller allows any user design to be field upgradable through PCIe. It can also eliminate the need for the USB platform cable during the design and development phase.
The base framework also provides the targeted (MIG generated) wrapper for the 1066Mbps (533MHz) DDR3 and 350MHz QDRII+ controllers. Memory mapped MDIO and I2C controllers are also integrated in the EFW to control and configure the PHYs and clock elements on HTG-616 module.
EFW also serves as the evaluation platform for the 10G low-latency and 40G Ethernet IP solutions. It allows the user to test the 10G and 40G Ethernet interface capabilities of the HTG-616 without any code development. User can then extend the Ethernet interfaces to user specific designs through the industry standard AXI4-Streaming interface. Full simulation libraries included in the EFW enables the user to simulate and test the Ethernet interfaces before licensing the solutions.EFW’s integrated (time limited) 4-channel 128-bit data path (@ 250MHz) block DMA controller along with the PCIe device drivers allows the user to implement and verify high speed data and packet applications on the HTG-616 module.
· Framework includes module targeted and hardware verified RTL blocks for:
o x8 PCIe Gen2 hard IP block with PCIe application interface and arbiter (for FPGA PCIe port1 only)
o AXI4-Lite master/arbiter for distributed control and configuration of various EFW blocks
o Two 1066Mbps/533MHz DDR3 controllers
o Two 350 MHz QDRII+ controllers
o Field upgradeable flash (FUp) controller for in-system field upgrade of the FPGA image through PCIe interface
o MDIO and I2C controllers
o DRP controller for run-time control and configuration of the GTH Transceivers
· Time limited (30min) synthesizable binaries and full simulation libraries for hardware verified Ethernet solutions up to 40Gbps:
o 40Gbps Ethernet using the direct QSFP+ interface on the module
o 10Gbps Low Latency Ethernet using the SFP+ interface on the module
· Time limited (30min) synthesizable binaries and full simulation libraries for hardware verified Multi-channel (4) 128-bit data path scatter-gather block DMA controller
· All modules with industry standard AXI-4 streaming interface for data path and AXI-4 Lite interface for control, configuration and memory interface
· Top level RTL interface wrapper for custom user design block for easy implementation of user logic
· Linux device drivers and API for PCIe interface
· A single unified GUI for entire EFW with scripting support