ASIC

16450 Configurable UART IP Core

General Description:

The D16450 is a soft IP Core of a Universal Asynchronous Receiver/Transmitter (UART) functionally identical to the TL16C450. D16450 performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt). D16450 includes a programmable baud rate generator that is capable of dividing the timing reference clock input by divisors of 1 to (2¹⁶-1), and producing a 16 × clock for driving the internal transmitter logic. Provisions are also included to use this 16 × clock to drive the receiver logic. The D16450 has complete MODEM control capability, and a processor-interrupt system. Interrupts can be programmed to the user's requirements, minimizing the computing required to handle the communications link.
D16450 includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
D16450 is a technology independent design that can be implemented in a variety of process technologies.

The separate BAUD CLK line allows to set an exact transmission speed, while the UART internal logic is clocked with the CPU frequency.

The core is perfect for applications, where the UART Core and microcontroller are clocked by the same clock signal and are implemented inside the same ASIC or FPGA chip, as well as for standalone implementation, where several UARTs are required to be implemented inside a single chip, and driven by some off-chip devices. Thanks to universal interface D16450 core implementation and verification are very simply, by eliminating a number of clock trees in complete system.

Key Features:

Software compatible with 16450 UART
Configuration capability
Separate configurable BAUD clock linee
Majority Voting Logic
Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from the serial data
Independently controlled transmit, receive, line status, and data set interrupts
False start bit detection
16 bit programmable baud generator
Independent receiver clock input
MODEM control functions (CTS, RTS, DSR, DTR, RI, and DCD)

Fully programmable serial-interface characteristics:
- 5-, 6-, 7-, or 8-bit characters
- Even, odd, or no-parity bit generation and detection
- 1-, 1½-, or 2-stop bit generation
- Internal baud generator
Complete status reporting capabilities
Line break generation and detection. Internal diagnostic capabilities:
- Loop-back controls for communications link fault isolation
- Break, parity, overrun, framing error simula-tion
Full prioritized interrupt system controls
As an option the UART Core can be equipped with the asynchronous input buffer allows correct communication with D16450 no matter how D16450 clock is related to microcontroller clock.
Fully synthesizable
Static synchronous design and no internal tri-states

Applications:

Serial Data communications applications
Modem interface
Embedded microprocessor boards

Units

Baud Generator

The UART contains a programmable 16 bit baud generator that divides clock input by a divisor in the range between 1 and (216–1). The output frequency of the baud generator is 16× the baud rate. The formula for the divisor is:

divisor=frequency/(16*baudrate)

Two 8-bit registers, called divisor latches DLL and DLM, store the divisor in a 16-bit binary format. These divisor latches must be loaded during initialization of the UART in order to ensure desired operation of the baud generator. When either of the divisor latches is loaded, a 16-bit baud counter is also loaded on the CLK rising edge following the write to DLL or DLM to prevent long counts on initial load.

Data Bus Buffer

The data Bus Buffer accepts inputs from the system bus and generates control signals for the other UART functional blocks. Address bus ADDR(2:0) selects one of the register to be read from/written into. Both RD and WR signals are active low. Both RD and WR are qualified by CS; RD and WR are ignored unless the UART has been selected by holding CS low.

Interrupt Controller

D16X50 UARTs consists fully prioritized interrupt system controller. It controls interrupt requests to the CPU and interrupt priority. Interrupt controller contains Interrupt Enable (IER) and Interrupt Identification (IIR) registers.

Modem Control Logic

Modem Control Logic controls the interface with the MODEM or data set (or a peripheral device emulating a MODEM).

Receiver Control

The D16X50 receiver has its own independent clock input RCLK. Receiving starts when the falling edge on Serial Input (SI) during IDLE State is detected. After starting the SI input is sampled every 16 RCLK cycles as it is shown in figure below. When the logic 1 state is detected during START bit it means that the False Start bit was detected and receiver back to the IDLE state.

Transmitter controller

Transmitter Control module controls transmission of written to THR (Transmitter Holding register) character via serial output SO. The new transmission starts on the next overflow signal of internal baud generator (the worst case delay is: 1 baudout cycle) after writing to THR. Transmission control contains THR register and transmitter shift register.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

D16450 implementation results for ALTERA devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	358	95
ACEX1K	-1	358	103
APEX20KE	-1	336	125
APEX20KC	-7	336	147
APEX II	-7	362	188
MERCURY	-5	338	188
STRATIX	-5	312	222
CYCLONE	-6	312	205

DI2CSB implementation results for LATTICE devices. The CPU features and Peripherals have been included.
Implementation	Speed Grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4E	-3	310/57	80
ORCA3T	-7	299/57	47

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info@hitechglobal.com
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