Microprocessor IP Core
D 68000 soft IP core is binary-compatible
with the industry standard 68000 32-bit microprocessor. D68000 has a
16-bit data bus and 24-bit ad-dress data bus. It is code compatible with
the MC68008 and is upward code compatible with the MC68010 virtual
extensions and the MC68020 32-bit implementation of the architecture.
D68000 has improved instructions set allows execution of a program with
higher performance than standard 68000 core.
D68000 is delivered with fully automated test-bench and complete set of
tests allowing easy package validation at each stage of SoC design flow.
A special testing platform has been built to run D68000 with
uCLinux Operating System. For more details please check
- Software compatible with industry standard 68000
- MULS, MULU take 28 clock periods
- DIVS, DIVU take 28 clock periods
- Optimized shifts and rotations
- Idle cycles removed to improve performance
- Shorter effective address calculation time
- Bus cycle timings identical to 68000
- 32 bit data and address registers
- 14 addressing modes:
- Data register direct
- Address register direct
- Register indirect
- Postincrement register indirect
- Predecrement register indirect
- Register indirect with offset
- Indexed register indirect with offset
- PC relative:
- Relative with offset
- Relative with index and offset
- Absolute data:
- Absolute short
- Absolute long
- Immediate data:
- Quick immediate
- 5 data types supported:
- bytes, words and long words
- Arithmetic Logic Unit includes:
- 8,16,32-bit arithmetic & logical operations
- 16x16 bit signed and unsigned multiplication
- 32/16 bit signed and unsigned division
- Boolean operations
- Interrupt controller:
- 7 priority levels interrupt controller
- Unlimited number of virtual interrupt sources
- Vectored and auto-vectored modes
- Memory interface includes:
- Up to 4 GB of address space
- 16-bit data bus
- Asynchronous bus control
- M6800 family synchronous interface
- 3- and 2- wire bus arbitration
- Supervisor and user modes
- Fully synthesizable
- Static synchronous design
Opcode Decoder – Performs an instruction opcode decoding
and the control functions for all other blocks.
Control Unit – Performs the core synchronization and data
flow control. This module manages execution of all instructions. Contains
SR (status register is consisted of two portions su-pervisor byte and user
byte) and its related logic.
Interrupt Controller – Interrupt Control module is
responsible for the interrupt manage system for the external &
internal interrupts and exceptions processing. It manages auto-vectored
interrupt cycles, priority resolving and correct vector numbers creation.
ALU – Arithmetic Logic Unit performs the arithmetic and
logic operations during execution of an instruction. It contains
accumulator and related logic such as arithmetic unit, logic unit,
multiplier and divider. BCD operation are exe-cuted in this unit and
condition code flags (N-negative, Z-zero, C-carry V-overflow) for most
Data registers – Contains 32-bit data registers D0 to D7
and related logic to perform byte, word and long data operations.
Memory Interface – Contains memory access related
registers It performs the memory addressing instructions code fetching and
data transfers. It is responsible for all external bus cycle actions such
as: read & write, repeated read & write, halt and resume of bus
cycles, bus arbitration provided by 3- and 2- wire system, correct bus and
address errors handling, wait states cycle insertion and M6800 synchronous
Address registers – Contains 32-bit A0 to A6 address
registers, two stack pointers USP (user SP) and SSP (Supervisor SP),
32-bit Program counter and related logic to perform word and long address
operations. An effective address operation are executed in this unit.
Shifter – Performs shifting operations for the
appropriate instructions, mainly for rotation, shift and bit operations.
clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..
Single Design license
allows implementation of IP Core in single
FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows
IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations
within a design, and number of manufactured chips are unlimited.
- One Year license
for Encrypted Netlist only
- Single Design
license for VHDL, Verilog source code called
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist
- VHDL Source Code or/and
- VERILOG Source Code or/and
- Encrypted, or plain text EDIF
VHDL & VERILOG test bench
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Installation notes
- HDL core specification
- IP Core implementation support
- 3 months maintenance (delivery of the IP Core updates, minor
and major versions changes, delivery of the documentation updates)
- Phone & email support
D68000 implementation results for ALTERA devices. The CPU features
and Peripherals have been included.
implementation results for XILINX devices.
The CPU features and Peripherals have been included.
Tel : + 1 408 781-7778
Fax: + 1 408 268-4173
2059 Camden Ave. Suite # 160
San Jose, CA 95124