ASIC

D8254 Programmable Interval Timer IP Core

General Description:
The D8254 is a programmable interval timer/counter, binary compatible with industry standard 82C54. The D8254 solves one of the most common problems in any micro-computer system, the generation of accurate time delays under software control. The D8254 can be used as a:

Real time clock
Even counter
Digital one-shot
Programmable rate generator
Square wave generator
Binary rate multiplier
Complex waveform generator
Complex motor controller

D8254 includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.
D8254 is a technology independent design that can be implemented in a variety of process technologies.

Key Features:

Three independent 16-bit counters
Six programmable Counter modes
- Interrupt on terminal count
- Hardware retriggerable One-Shot
- Rate Generator
- Square wave mode
- Software triggered strobe
- Hardware triggered strobe

Binary or BCD counting
Status Read Back Command
Simple interface allows easy connection to microcontrollers
Fully synthesizable
Static design and no internal tri-states

Applications:

Embedded microprocessor boards

Units

Control Word

The Control Word Register is selected by the Read/Write Logic when ADDR(1:0) = 11. If the CPU then does a write operation to the D8254, the data is stored in the Control Word Register and is interpreted as a Control Word used to define the operation of the Counters.

Data Bus Buffer

The 8-bit buffer is used to interface the D8254 to the system bus.

Read Write Logic

The Read/Write Logic accepts inputs from the system bus and generates control signals for the other functional blocks of the D8254. ADDR(1:0) select one of the three counters or the Control Word Reg-ister to be read from/written into. A "low'' on the RD input tells the D8254 that the CPU is reading one of the counters. A "low'' on the WR input tells the D8254 that the CPU is writing either a Control Word or an initial count. Both RD and WR are qualified by CS; RD and WR are ignored unless the 82C54 has been selected by holding CS low. The WR and CLK signals should be synchronous. This is accomplished by using a CLK input signal to the D8254 counters which is a derivative of the system clock source. Another technique is to externally synchronize the WR and CLK input signals. This is done by gating WR with CLK.

Counter 0

All three Counters (0, 1, 2) are functionally identical and fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:

Interrupt on terminal count
Hardware retriggerable One-Shot
Rate Generator
Square wave mode
Software triggered strobe
Hardware triggered strobe

Counter 1

All three Counters (0, 1, 2) are functionally identical and fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:

Interrupt on terminal count
Hardware retriggerable One-Shot
Rate Generator
Square wave mode
Software triggered strobe
Hardware triggered strobe

Counter 2

All three Counters (0, 1, 2) are functionally identical and fully independent. Each can work as a 16 bit wide Binary or BCD counter, in one of the six available modes:

Interrupt on terminal count
Hardware retriggerable One-Shot
Rate Generator
Square wave mode
Software triggered strobe
Hardware triggered strobe

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

D8254 implementation results for ALTERA devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	540	90
ACEX1K	-1	535	90
APEX20KE	-1	511	88
APEX20KC	-7	511	120
APEX II	-7	572	143
MERCURY	-5	541	201
STRATIX	-5	512	188
CYCLONE	-6	512	165

D8254 implementation results for XILINX devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-II	-6	349	79
VIRTEX	-6	349	78
VIRTEX-E	-8	349	91
VIRTEX-II	-6	346	115

D8254 implementation results for LATTICE devices. The CPU features and Peripherals have been included.
Implementation	Speed Grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ispXPGA	-4	712 / 211	59
ORCA4E	-3	660 / 116	48

Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com
2059 Camden Ave. Suite # 160
San Jose, CA 95124
U.S.A

Units

Control Word

Data Bus Buffer

Read Write Logic

Counter 0

Counter 1

Counter 2

Licensing Options:

Comprehensible and clearly defined licensing methods without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.

Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.

- Single Design license for VHDL, Verilog source code called HDL Source - Encrypted, or plain text EDIF called Netlist - Unlimited Designs license for HDL Source or Netlist

Deliverables:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist