ASIC

CORDIC Processor IP Core

General Description:
The DCORDIC uses the CORDIC algorithm to compute trigonometric, reverse trigonometric, hyperbolic and reverse hyperbolic functions. It supports sine, cosine, arcus tangent functions for hyperbolic and trigonometric systems. Logarithm, square root and exponent functions can also be computed. It supports fixed point 24-bit numbers.
DCORDIC is a technology independent design that can be implemented in a variety of process technologies.

Key Features:

24-bit precision (IEEE-754 single preci-sion real mantissa format)
4-ulp accuracy (34-bit internal registers)
Fully configurable
Performs the following functions:
- sin(x), cos(x)
- sinh(x), cosh(x)
- arctan(x)
- arctanh(x)
- ln(x), e^x, sqrt(x)
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

Applications:

Math coprocessors
DSP algorithms
Embedded arithmetic coprocessor
Fast data processing & control

Units

Shifters

It performs shifting operations in successful iterations. Number of shifts vary and depend on internal iteration cycle and computed functions.

Registers

It contains all data registers hold temporary operation results as well as final results. Input arguments are written to this register also.

Control Unit

It maintains control operation on Registers module, Shifters module and ROM unit while busy is active.

Interface

It performs communication between internal CORDIC modules and external devices. Signalizes when output registers contain a valid result.

ROM

It stores constant coefficients used for hyperbolic and trigonometric operations.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

Data Sheet:
ASICS Implementation

Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com
2059 Camden Ave. Suite # 160
San Jose, CA 95124
U.S.A

Units

Shifters

Registers

Control Unit

Interface

ROM

Licensing Options:

Comprehensible and clearly defined licensing methods without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.

Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.

- Single Design license for VHDL, Verilog source code called HDL Source - Encrypted, or plain text EDIF called Netlist - Unlimited Designs license for HDL Source or Netlist

Deliverables:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist