DF 6811 IP Core (8-bit FAST Microcontrollers Family)

General Description:
The DF 6811 is a advanced 8-bit MCU IP Core with highly sophisticated, on chip peripheral capabilities. DF 6811 soft core is binary-compatible with the industry standard 68HC11 8-bit microcontroller and can achieve a performance 45-100 million instructions per second. There are two configurations of DF6811:
- Harvard - where data and program buses are separated
- von Neumann - with common program and data bus.
DF6811 has FAST architecture that is 4.4 times faster compared to original implementation. Core in standard configuration has integrated on chip major peripheral functions.

There are two serial interfaces: an asynchronous serial communications interface (SCI) and a separate synchronous serial peripheral interface (SPI). The main 16-bit, free-running timer system has three input capture lines, five output-compare lines, and a real-time interrupt function. An 8-bit pulse accumulator subsystem can count external events or measure external periods.

Self-monitoring circuitry is included on-chip to protect against system errors. A computer operating properly (COP) watchdog system protects against software failures. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected.

Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6811 IP Core especially attractive for automotive and battery-driven applications.

The DF6811 have built in the development support features designed into DF6811. The LIR signal is intended as a debugging aid. This signal is driven to active low for the first bus cycle of each new instruction, making it easy to reverse assemble (disassemble) instructions from the display of a logic analyzer.

DF6811 is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

Each DCD's DF68XX Core has built in support for DCD Hardware Debug System called DoCDTM. It's a real-time hardware debugger provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers DoCDTM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...

CPU Features:

FAST architecture, 4.4 times faster than the original implementation
Software compatible with industry standard 68HC11
Configurable Harvard or Von Neumann architectures
10 times faster multiplication
16 times faster division
256 bytes of remapped System Function Registers space (SFRs)
Up to 16M bytes of Data Memory
Up to 64K bytes of Code Memory
De-multiplexed Address/Data Bus to allow easy memory connection

Two power saving modes: STOP, WAI
Ready pin allows Core to operate with slow program and data memories.
Fully synthesizable
Static synchronous design
No internal reset generator or gated clock
Positive edge clocking and no internal tri-states
Scan test ready
1 GHz of virtual clock frequency compared to original implementation

Peripherals:

DoCD™ debug unit
- Processor execution control
- Read-write all processor contents
- Hardware execution breakpoints
- Three wire communication interface
Four 8-bit I/O Ports
Extended Interrupt Controller
- 20 interrupt sources
- 17 priority levels
Main16-bit timer/counter system
- 16 bit free running counter
- Four stage programmable prescaller
- Timer clocked by internal source
- Real Time Interrupt
16-bit Compare/Capture Unit
- Three independent input-capture functions
- Five output-compare channels
- Events capturing
- Pulses generation
- Digital signals generation
- Gated timers
- Sophisticated comparator
- Pulse width modulation
- Pulse width measuring

8-bit Pulse accumulator
- Two major modes of operation
  - Simple event counter
  - Gated time accumulation
- Clocked by internal source or external pin
Full-duplex UART - SCI
- Standard Non-return to Zero format (NRZ)
- 8 or 9 bit data transfer
- Integrated BAUD Rate generator
- Enhanced receiver data sampling technique
- Noise,Overrun and Framing errors detection
- IDLE and BREAK characters generation
- Wake-up block to recognize UART wake-up from IDLE
- Three SCI Related interrupts
SPI – Master and Slave Serial Peripheral Interface
- Supports speeds up ¼ of system clock
  - Mode fault error
  - Write collision error
- Software selectable polarity and phase of serial clock SCK
- System errors detection
- Allows operation from a wide range of system clock frequencies
- Interrupt generation

Design Features:

- One global system clock
- Synchronous reset
- All asynchronous input signals are synchronized before internal use
- Synchronous logic without microcode

Configuration:

The following parameters of the DF6811 core can be easy adjusted to requirements of dedicated application and technology. Configuration of the core can be prepared by effortless changing appropriate constants in package file. There is no need to change any parts of the code.

Architecture	Harvard von Neuman
Memories type	synchronous asynchronous
Data memory size	64kB 16MB
Memories WAIT states	used unused
Interrupt controller	used unused
Power saving STOP Mode	used unused
DoCD^TM debug unit	used unused

Units

Opcode Decoder
It performs an instruction opcode decoding and the control functions for all other blocks.

Control Unit
It performs the core synchronization and data flow control. This module manages execution of all instructions.

ALU
Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (A, Condition Code Register (CCREG), and related logic such as arithmetic unit, logic unit, multiplier and divider.

Interrupt Controller

DF6811 has implemented 17-level interrupt priority control. External interrupt pins are activated at low level(XIRQ,IRQ pins) or falling edge (IRQ pin). External interrupt requests by IRQ, XIRQ are sampled each 1 system clock at the rising edge of CLK. The DF6811 peripheral systems generate maskable interrupts, which are recognized only if the global interrupt mask bit (I) in the CCR is cleared. Maskable interrupts are prioritized according to default arrangement (look at the table below) established during reset. However any one source may be elevated to the highest maskable priority position using HPRIO register. When interrupt condition occurs, an interrupt status flag is set to indicate the condition.

Bus Controller

Program Memory, Data Memory & SFR's (Special Function Register) interface controls access into the program and data memories and special registers. It contains Program Counter (PC), Stack Pointer (SP) register, INIT register (INIT), Data Page Pointer (DPP), and related logic.

Timer with Compare Capture

This timer system is based on a free-running 16-bit counter with a 4-stage programmable prescaler. A timer overflow function allows software to extend the timing capability of the system beyond the 16-bit range of the counter. Three independent input-capture functions are used to automatically record the time when a selected transition is detected at a respective timer input pin. Five output-compare functions are included for generating output signals or for timing software delays. Since the input-capture and output-compare functions may not be familiar to all users, these concepts are explained in greater detail.
A programmable periodic interrupt circuit called RTI is tapped off of the main 16-bit timer counter. Software can select one of four rates for the RTI, which is most commonly used to pace the execution of software routines. The COP watchdog function is closely related to the main timer in that the clock input to the COP system (clk*2^17) is tapped off the free-running counter chain.
The timer subsystem involves more registers and control bits than any other subsystem on the MCU. Each of the three input-capture func-tions has its own 16-bit time capture latch (input-capture register) and each of the five output-compare functions has its own 16-bit compare register. All timer functions, including the timer overflow and RTI, have their own interrupt controls and separate interrupt vectors. Additional control bits permit software to control the edge(s) that trigger each input-capture function and the automatic actions that result from output-compare functions. Although hardwired logic is included to automate many timer activities, this timer architecture is essentially a software-oriented system. This structure is easily adaptable to a very wide range of applications although it is not as efficient as dedicated hardware for some specific timing applications.

Watchdog Timer

A programmable periodic interrupt circuit called RTI is tapped off of the main 16-bit timer counter. Software can select one of four rates for the RTI, which is most commonly used to pace the execution of software routines. The COP watchdog function is closely related to the main timer in that the clock input to the COP system (clk*2^17) is tapped off the free-running counter chain.

SCI

The SCI is a full-duplex UART type asynchronous system, using standard non return to zero (NRZ) format : 1 start bit, 8 or 9 data bits and a 1 stop bit. The Core resynchronizes the receiver bit clock on all one to zero transitions in the bit stream. Therefore differences in baud rate between the sending device and the SCI are not as likely to cause reception errors. Three logic samples are taken near the middle of data bit time, and majority logic decides the sense for the bit. For the start and stop bits seven logic samples are taken. Even if noise causes one of these samples to be incorrect, the bit will still be received correctly. The receiver also has the ability to enter a temporary standby mode (called receiver wakeup) to ignore messages intended for a different receiver. Logic automatically wakes up the receiver in time to see the first character of the next message. This wakeup feature greatly reduces CPU overhead in multidrop SCI networks. The SCI transmitter can produce queued characters of idle (whole characters of all logic 1) and break (whole characters of all logic 0). In addition to the usual transmit data register empty (TDRE) status flag, this SCI also provides a transmit complete (TC) indication that can be used in applications with a modem.

SPI Unit

It’s a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to become bus master.

Pulse Accumulator

This system is based on an 8-bit counter and can be configured to operate as a simple event counter or for gated time accumulation. Unlike the main timer, the 8-bit pulse accumulator counter can be read or written at any time (the 16-bit counter in the main timer cannot be written). Control bits allow the user to configure and control the pulse accumulator subsystem. Two maskable interrupts are associated with the system, each having its own controls and interrupt vector. The PAI pin associated with the pulse accumulator can be configured to act as a clock (event counting mode) or as a gate signal to enable a free-running E divided by 64 clock to the 8-bit counter (gated time accumulation mode). The alternate functions of the pulse accumulator input (PAI) pin present some in-teresting application possibilities.

I/O Ports

All ports are 8-bit general-purpose bi-directional I/O system. The PORTA, PORTB, PORTC, PORTD data registers have their corresponding data direction registers DDRA, DDRB, DDRC, DDRD to control ports data flow. It assures that all ports have full I/O selectable registers. Writes to any ports pins cause data to be stored in the data registers. If any port pins are configured as output then data registers are driven out of those pins. Reads from port pins configured as input causes that input pin is read. If port pins is configured as output, during read data register is read.
Writes to any ports pins not configured as outputs do not cause data to be driven out of those pins, but the data is stored in the output registers. Thus, if the pins later become outputs, the last data written to port will be driven out the port pins.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

DF6811 implementation results for ALTERA devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	3023	33
ACEX1K	-1	3023	33
APEX20KE	-1	2972	39
APEX20KC	-7	2972	43
APEX II	-7	3092	50
MERCURY	-5	3095	67
STRATIX	-5	2958	62
CYCLONE	-6	2957	58

DF6811 implementation results for XILINX devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-II	-6	1515	38
SPARTAN-IIE	-7	1515	42
VIRTEX	-6	1515	36
VIRTEX-E	-8	1515	45
VIRTEX-II	-6	1515	51
VIRTEX-II pro	-7	1515	56

DF6811 implementation results for LATTICE devices. The CPU features and Peripherals have been included.
Implementation	Speed Grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4E	-3	3050 / 830	30

Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com
2059 Camden Ave. Suite # 160
San Jose, CA 95124
U.S.A

Design Features: - One global system clock - Synchronous reset - All asynchronous input signals are synchronized before internal use - Synchronous logic without microcode

Units

Opcode Decoder It performs an instruction opcode decoding and the control functions for all other blocks.

Control Unit It performs the core synchronization and data flow control. This module manages execution of all instructions.

ALU Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (A, Condition Code Register (CCREG), and related logic such as arithmetic unit, logic unit, multiplier and divider.