DF 6811CPU (8-bit FAST Microcontrollers) IP Core

General Description:
The 6811CPU is a advanced 8-bit MCU IP Core. DF6811CPU soft core is binary-compatible with the industry standard 68HC11 8-bit microcontroller and can achieve a performance 45-100 million instructions per second. There are two configurations of DF6811CPU:

- Harvard - where data and program buses are separated
- Von Neumann - with common program and data bus.

The DF6811CPU has FAST architecture that is 4.4 times faster compared to original implementation.

Self-monitoring circuitry is included on-chip to protect against system errors. An illegal opcode detection circuit provides a non-maskable interrupt if illegal opcode is detected.

Two software-controlled power-saving modes, WAIT and STOP, are available to conserve additional power. These modes make the DF6811CPU IP Core especially attractive for automotive and battery-driven applications.

The DF6811CPU have built in the development support features designed into DF6811CPU. The LIR signal is intended as a debugging aid. This signal is driven to active low for the first bus cycle of each new instruction, making it easy to reverse assemble (disassemble) instructions from the display of a logic analyzer.

DF6811CPU is fully customizable, which means it is delivered in the exact configuration to meet users’ requirements. There is no need to pay extra for not used features and wasted silicon. It includes fully automated testbench with complete set of tests allowing easy package validation at each stage of SoC design flow.

Each DCD's DF68XX Core has built in support for DCD Hardware Debug System called DoCD™. It is a real-time hardware debugger provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers DoCD provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, SFRs including user defined peripherals, data and program memories. More details about DCD on Chip Debugger...

CPU Features:

FAST architecture, 4.4times faster than the original implementation
Software compatible with industry standard 68HC11
Configurable Harvard or Von Neumann architectures
10 times faster multiplication
16 times faster division
256 bytes of remapped System Function Registers space (SFRs)
Up to 16M bytes of Data Memory
De-multiplexed Address/Data Bus to allow easy memory connection

Two power saving modes: STOP, WAI
READY pin allows the CPU to operate with slow program and data memories.
Fully synthesizable
Static synchronous design
No internal reset generator or gated clock
Positive edge clocking and no internal tri-states
Scan test ready
1 GHz of virtual clock frequency compared to original implementation

Peripherals:

Interrupt Controller

- 3 interrupt sources

DoCD™ debug unit
- Processor execution control
- Read-write all processor contents
- Hardware execution breakpoints
- Three wire communication interface

Design Features

One global system clock
Synchronous reset
All asynchronous input signals are synchronized before internal use
Synchronous logic without microcode

Units

Control Unit

It performs the core synchronization and data flow control. This module manages execution of all instructions.

Opcode Decoder

It performs an instruction opcode decoding and the control functions for all other blocks.

ALU

Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (A, B), Condition Code Register (CCREG), and related logic such as arithmetic unit, logic unit, multiplier and divider.

Interrupt Controller

DF6811CPU has implemented only external interrupts from pins IRQ and XIRQ. The interrupts are acti-vated at low level (XIRQ,IRQ pins) or falling edge (IRQ pin) and are sampled each 1 system clock at the rising edge of CLK.

Bus Controller

Program Memory, Data Memory & SFR's (Special Function Register) interface controls access into the program and data memories and special registers. It contains Program Counter (PC), Stack Pointer (SP) register, INIT register (INIT), Data Page Pointer (DPP), and related logic.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

Performance:

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	1785	32
ACEX1K	-1	1785	34
APEX20KE	-1	1809	42
APEX20KC	-7	1809	46
APEX II	-7	1849	50
MERCURY	-5	1808	61
STRATIX	-5	1834	60
CYCLONE	-6	1834	58

DF6811CPU implementation results for ALTERA devices. All features have been included.

Implementation	Speed grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-II	-6	1312	31
SPARTAN-IIE	-7	1319	34
SPARTAN-III	-5	1312	44
SPARTAN-IIIE	-4	1322	31
VIRTEX	-6	1321	31
VIRTEX-E	-8	1323	35
VIRTEX-II	-6	1318	62
VIRTEX-II pro	-7	1321	73
VIRTEX-IV	-12	1291	80

DF6811CPU implementation results for XILINX devices. All features have been included.

Implementation	Speed grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4E	-3	2504/404	34
XP	-5	2598/374	39
ECP	-5	2598/374	42
EC	-5	2598/374	42

DF6811CPU implementation results for LATTICE devices. All features have been included.

Units

Control Unit

Opcode Decoder

ALU

Interrupt Controller

Bus Controller

Licensing Options:

Comprehensible and clearly defined licensing methods without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.

Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.

- Single Design license for VHDL, Verilog source code called HDL Source - Encrypted, or plain text EDIF called Netlist - Unlimited Designs license for HDL Source or Netlist

Deliverables:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist