FPAU Floating Point
Arithmetic Unit IP Core
DFPAU IP Core uses the specialized algorithms
to compute arithmetic functions. It supports addition, subtraction,
multiplication, division, square root, comparison, absolute value, and
change sign of a number. The input numbers format is according to IEEE-754
standard single precision real numbers. DFPAU is prepared to use with 8-,
16- and 32-bit processors. Trigonometric functions are supported
indirectly, because they are computed as set of add, multiply and divide
operations by software subroutines.
DFPAU is a technology independent design that can be implemented in a
variety of process technologies.
- Direct replacement for C
float software functions such as: +, -, *, /,==, !=,>=, <=,
- C interface supplied for all popular compilers: GNU
C/C++, 8051 compilers
- No programming required
- IEEE-754 Single precision real format support – float
- Flexible arguments and result registers location
- Performs the following functions:
- FADD, FSUB – addition, subtraction
- FMUL, FDIV – multiplication, division
- FSQRT – square root
- FCHS, FABS – change of sign, absolute value
- FXAM – examine input data
- FUCOM – comparison
- Exceptions built-in routines
- Masks each exception indicator:
- Precision lack PE
- Underflow result UE
- Overflow result OE
- Invalid operand IE
- Division by zero ZE
- Denormal operand DE
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Math coprocessors
- DSP algorithms
- Embedded arithmetic coprocessor
- Fast data processing & control
It performs the numbers analyze against IEEE-754 standard
compliance. Information about the data classes are passed as result to
appro-priate internal module.
It performs operations on exponent part of number. The
addition, subtraction, shifting, comparison and conversion operations are
executed in this module. It contains exponents and work registers.
It is an interface between external device and DFPAU
internal 32-bit modules. It contains data, control and status registers.
It can be configured to work with 8-, 16- and 32-bit processors.
1 - data bus can be configured as 8-, 16- or 32- bit depends
on processor’s bus size
2 - address bus is aligned to work with 8- (3:0), 16- (3:1) or
32- (4:2) bit processors
It performs operations on mantissa part of number. The
addition, subtraction, multiplication, division, square root, comparison
and conversion operations are executed in this module. It contains
mantissas and work registers.
It performs mantissa shifting during normalization,
denormalization operations. Information about shifted-out bits are stored
for rounding process.
It manages execution of all instructions and internal
operation required to execute particular function.
clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..
Single Design license
allows implementation of IP Core in single
FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows
IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations
within a design, and number of manufactured chips are unlimited.
- One Year license
for Encrypted Netlist only
- Single Design
license for VHDL, Verilog source code called
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist
- VHDL Source Code or/and
- VERILOG Source Code or/and
- Encrypted, or plain text EDIF
VHDL & VERILOG test bench
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Installation notes
- HDL core specification
- IP Core implementation support
- 3 months maintenance (delivery of the IP Core updates, minor
and major versions changes, delivery of the documentation updates)
- Phone & email support
DFPAU implementation results for ALTERA devices. The CPU features
and Peripherals have been included.
implementation results for XILINX devices.
The CPU features and Peripherals have been included.
implementation results for LATTICE devices. The CPU features
and Peripherals have been included.