FPCOMP Floating Point Comparator Unit IP Core

General Description:

The DFPCOMP IP Core compares two arguments. The input numbers format is according to IEEE-754 standard. DFPCOMP supports single precision real numbers. Compare operation was pipelined up to 1 level. Input data are fed every clock cycle. The first result appears after 1 clock period latency and next results are available each clock cycle. Full IEEE-754 unordered compare function is included.
DFPCOMP is a technology independent design that can be implemented in a variety of process technologies.

Key Features:

Full IEEE-754 compliance
Single precision real format support
Simple interface
No programming required
1 level pipeline

Results available at every clock
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

Applications:

Math coprocessors
DSP algorithms
Embedded arithmetic coprocessor
Fast data processing & control

Units

Arguments Checker

It performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit.

Main FP Pipelined Unit

It performs floating point compare function. Gives the complex information about the results and makes final flags settings.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

DFPCOMP implementation results for ALTERA devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	139	52
APEX20K	-1	136	45
APEX20KE	-1	136	58
APEX20KC	-7	136	68
APEX II	-7	136	88
MERCURY	-5	140	129
STRATIX	-5	136	125
CYCLONE	-6	137	114
ACEX1K	-1	139	50

DFPCOMP implementation results for XILINX devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-II	-6	76	71
SPARTAN-IIE	-7	72	74
VIRTEX	-6	70	64
VIRTEX-E	-8	71	76
VIRTEX-II	-5	70	116
VIRTEX-II pro	-7	70	149

DFPCOMP implementation results for LATTICE devices. The CPU features and Peripherals have been included.
Implementation	Speed Grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4E	-3	224/37	47
ispXPGA	-4	160/51	100

Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com
2059 Camden Ave. Suite # 160
San Jose, CA 95124
U.S.A

Units

Arguments Checker

Main FP Pipelined Unit

Licensing Options:

Comprehensible and clearly defined licensing methods without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.

Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.

- Single Design license for VHDL, Verilog source code called HDL Source - Encrypted, or plain text EDIF called Netlist - Unlimited Designs license for HDL Source or Netlist

Deliverables:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist