ASIC

FPDIV Floating Point Pipelined Divider Unit IP Core

General Description:

The DFPDIV IP Core uses the pipelined mathematics algorithm to divide two arguments. The input numbers format is according to IEEE-754 standard. DFPDIV supports single precision real number. Divide operation was pipelined up to 15 levels. Input data are fed every clock cycle. The first result appears after 15 clock periods latency and next results are available each clock cycle. Full IEEE-754 precision and accuracy are included.
DFPADD is a technology independent design that can be implemented in a variety of process technologies.

Key Features:

Full IEEE-754 compliance
Single precision real format support
Simple interface
No programming required
15 levels pipeline

Overflow, underflow and invalid operation flags
Full accuracy and precision
Results available at every clock
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

Applications:

Math coprocessors
DSP algorithms
Embedded arithmetic coprocessor
Fast data processing & control

Units

Main FP Pipelined Unit

It performs floating point divide function. Gives the complex information about the results and makes final flags settings.

Arguments Checker

It performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit.

Result Composer

It performs floating point to integer conversion. Gives the complex information about the results to Result Composer module.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

DFPDIV implementation results for ALTERA devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	3312	34
APEX20K	-1	3454	35
APEX20KE	-1	3454	32
APEX20KC	-7	3454	42
APEX II	-7	3454	47
MERCURY	-5	3226	75
STRATIX	-5	2941	75
CYCLONE	-6	2941	67
ACEX1K	-1	3312	32

DFPDIV implementation results for XILINX devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-II	-6	1672	46
SPARTAN-IIE	-7	1672	44
VIRTEX	-6	1671	43
VIRTEX-E	-8	1667	50
VIRTEX-II	-5	1723	57
VIRTEX-II pro	-7	1723	72

DFPDIV implementation results for LATTICE devices. The CPU features and Peripherals have been included.
Implementation	Speed Grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4E	-3	2996/479	27
ispXPGA	-4	3132/1063	41

Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com
2059 Camden Ave. Suite # 160
San Jose, CA 95124
U.S.A

Units

Main FP Pipelined Unit

Arguments Checker

Result Composer

Licensing Options:

Comprehensible and clearly defined licensing methods without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.

Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.

- Single Design license for VHDL, Verilog source code called HDL Source - Encrypted, or plain text EDIF called Netlist - Unlimited Designs license for HDL Source or Netlist

Deliverables:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist