Performance 8-bit RISC Microcontroller IP Core
The DFPIC1655X is a low-cost, high
performance, 8-bit, fully static soft IP Core, dedicated for operation
with fast memory (typically on-chip). The core has been de-signed
with a special concern about low power consumption.
The DFPIC1655X is software compatible with the industry standard PIC16C554
and PIC16C558. It employs a modified RISC architecture (2 times faster
than original implementation).
The DFPIC1655X have enhanced core features, configurable hardware stack,
and multiple internal and external interrupt sources. The separate
instruction and data buses allow a 14 bit wide instruction word with the
separate 8-bit wide data. The DFPIC1655X typically achieve a 2:1 code
compression and a 8:1 speed improvement over other 8-bit microcontrollers
in their class.
The power-down mode SLEEP allow user to reduce power consumption. User can
wake up the controller from SLEEP through several external and internal
interrupt and reset. An integrated Watchdog Timer with it's own clock
signal provides protection against software lock-up.
The DFPIC1655X Microcontroller fits perfectly in applications ranging from
high-speed automotive and appliance motor control to low-power remote
transmitters/receivers, pointing devices and telecom processors. Built-in
power save mode and small used area in programmable devices make this IP
perfect for applications applications with space and power consumption
DFPIC165X is delivered with fully automated testbench and complete
set of tests allowing easy package validation at each stage of SoC
- Software compatible with industry standard PIC16C55X
- Harvard RISC architecture
- 2 times faster compared to original implementation
- 35 instructions
- 14 bit wide instruction word
- Up to 512 bytes of internal Data Memory
- Up to 64K bytes of Program Memory
- Configurable hardware stack
- Power saving SLEEP mode
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Technology independent HDL Source Code
- Two 8 bit I/O ports
- Two 8-bit corresponding TRIS
- Interrupt feature on PORTB(7:4)
- Timer 0
- 8-bit timer/counter
- Readable and Writable
- 8-bit software programmable
- Internal or external clock select
- Interrupt generation on timer
- Edge select for external clock
- Watchdog Timer
- Configurable Time out period
- 7-bit software programmable
- Dedicated independent Watchdog
- Interrupt Controller
- Three individually maskable
- External interrupt INT
- Timer Overflow interrupt
- Port B[7:4] change interrupt
It performs the core synchronization and data flow control.
This module manages execution of all instructions. Performs decode and
control functions for all other blocks. It contains program counter (PC)
and hardware stack.
It’s a configurable hardware stack. The stack space is
not a part of either program or data space and the stack pointer is not
readable or writable. The PC is pushed onto the stack when CALL
instruction is executed or an interrupt causes a branch. The stack is
popped while RETURN, RETFIE and RETLW instruction execution. The stack
operates as a circular buffer. This means that after the stack has been
pushed eight times, the ninth push overwrites the value that was stored
from the first push..
Block contains DFPIC1655X’s general purpose I/O ports and
data direction registers (TRIS). The DFPIC1655X has two 8-bit full
bi-directional ports PORT A, PORT B. Read and write accesses to the I/O
port are performed via their corresponding SFR’s PORTA, PORTB. The
reading instruction always reads the status of Port pins. Writing
instructions always write into the Port latches. Each port’s pin has an
corresponding bit in TRISA and TRISB registers. When the bit of TRIS
register is set this means that the corresponding bit of port is
configured as an input (output drivers are set into the High Impedance).
Interrupt Controller module is responsible for interrupt
manage system for the external and internal interrupt sources. It contains
interrupt related register called INTCON There are three interrupt
The interrupt control register INTCON records individual
interrupt requests in flag bits. A global interrupt enable bit, GIE
enables all unmasked interrupts. Each interrupt source has an individual
enable bit, which can enable or disable corresponding interrupt. When an
interrupt is responded to, the GIE is cleared to disable any further
interrupt, the return address is pushed into the stack and the PC is
loaded with 0004h. The interrupt flag bits must be cleared in software
before re-enabling interrupts.
- External interrupt INT
- TMR0 overflow interrupt
- PORTB change interrupt (pins B[7:4])
It performs interface functions between Data Memory and
DFPIC1655X internal logic. It assures correct Data memory addressing and
data transfers. The DFPIC1655X supports two addressing modes: direct or
indirect. In Direct Addressing the 9-bit direct address is computed from
RP(1:0) bits (STATUS) and 7 least significant bits of instruction word.
Indirect addressing is possible by using the INDF register. Any
instruction using INDF register actually accesses data pointed to by the
file select register FSR. Reading INDF register indirectly will produce
00h. Writing to the INDF register indirectly results in a no-operation. An
effective 9-bit address is obtained by concatenating the IRP bit (STATUS)
and the 8-bit FSR register.
Main system’s timer and prescaler. This timer operates in
two modes: 8-bit timer or 8-bit counter. In the “timer mode”, timer
registers are incremented every 4 CLK periods. When the prescaler is
assigned into the TIMER prescale ration can be divided by 2, 4, ..., 256.
In the “counter mode” the timer register is incremented every falling
or rising edge of T0CKI pin, dependent on T0SE bit in OPTION register.
The watchdog timer is a free running timer. WDT has own
clock input separate from system clock. It means that the WDT will run
even if the system clock is stopped by execution of SLEEP instruction.
During normal operation, a WDT timeout generates a Watchdog reset. If the
device is in SLEEP mode the WDT timeout causes the device to wake-up and
continue with normal operation.
Arithmetic Logic Unit performs arithmetic and logic
operations during execution of an instruction. This module contains work
register (W) and Status register.
clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..
Single Design license
allows implementation of IP Core in single
FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows
IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations
within a design, and number of manufactured chips are unlimited.
- One Year license
for Encrypted Netlist only
- Single Design
license for VHDL, Verilog source code called
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist
- VHDL Source Code or/and
- VERILOG Source Code or/and
- Encrypted, or plain text EDIF
VHDL & VERILOG test bench
- Active-HDL automatic simulation macros
- ModelSim automatic simulation macros
- Tests with reference responses
- Installation notes
- HDL core specification
- IP Core implementation support
- 3 months maintenance (delivery of the IP Core updates, minor
and major versions changes, delivery of the documentation updates)
- Phone & email support
implementation results for ALTERA devices. The CPU features
and Peripherals have been included.
implementation results for XILINX devices.
The CPU features and Peripherals have been included.
implementation results for LATTICE devices. The CPU features
and Peripherals have been included.
Tel : + 1 408 781-7778
Fax: + 1 408 268-4173
2059 Camden Ave. Suite # 160
San Jose, CA 95124