DFPMU Floating Point Mathematics Unit

ASIC

FPMU Floating Point Mathematics Unit IP Core

General Description:

DFPMU IP Core uses the specialized CORDIC and standard algorithms to compute math functions. It supports addition, subtraction, multiplication, division, square root, comparison, absolute value, change sign of a number and trigonometric functions: sine, cosine, tangent and arctangent. It has built-in conversion instructions from integer type to floating point type and vice versa. The input numbers format is according to IEEE-754 standard. DFPMU supports single precision real numbers, 16-bit and 32-bit integers. DFPMU is prepared to use with 8-, 16- and 32-bit processors.
DFPMU is a technology independent design that can be implemented in a variety of process technologies.

Key Features:

Direct replacement for C float software functions such as: +, -, *, /,==, !=,>=, <=, <, >
C interface supplied for all popular compilers: GNU C/C++, 8051 compilers
No programming required
IEEE-754 Single precision real format support – float type
16-bit word and 32-bit short integers format supported – integer types
Flexible arguments and result registers location
Performs the following functions:
- FADD, FSUB – addition, subtraction
- FMUL, FDIV – multiplication, division
- FSQRT – square root
- FCHS, FABS – change of sign, absolute value
- FXAM – examine input data
- FUCOM – comparison
- FSIN, FCOS – sine, cosine
- FTAN – tangent
- FATAN – arctangent
- FILDW, FILD – 16-bit, 32-bit integer to float
- FISTW, FIST – float to 16-bit, 32-bit integer

Exceptions built-in routines
Masks each exception indicator:
- Precision lack PE
- Underflow result UE
- Overflow result OE
- Invalid operand IE
- Division by zero ZE
- Denormal operand DE
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

Applications:

Math coprocessors
DSP algorithms
Embedded arithmetic coprocessor
Fast data processing & control

Units

Align

It performs the numbers analyze against IEEE-754 standard compliance. Information about the data classes are passed as result to appro-priate internal module.

Control Unit

It manages execution of all instructions and internal operation required to execute particular function.

Exponent

It performs operations on exponent part of number. The addition, subtraction, shifting, comparison and conversion operations are executed in this module. It contains exponents and work registers.

CORDIC

CORDIC performs trigonometric operations on input data. The sine, cosine, tangent and arctangent operations are executed in this module. It contains three work registers.

Interface

It is an interface between external device and DFPAU internal 32-bit modules. It contains data, control and status registers. It can be configured to work with 8-, 16- and 32-bit processors.

^{1 - data bus can be configured as 8-, 16- or 32- bit depends
on processor’s bus size}
^{2 - address bus is aligned to work with 8- (3:0), 16- (3:1) or
32- (4:2) bit processors}

Mantissa

It performs operations on mantissa part of number. The addition, subtraction, multiplication, division, square root, comparison and conversion operations are executed in this module. It contains mantissas and work registers.

Shifter

It performs mantissa shifting during normalization, denormalization operations. Information about shifted-out bits are stored for rounding process.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

DFPMU implementation results for ALTERA devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	4973	40
APEX20K	-1	4836	42
APEX20KE	-1	4863	44
APEX20KC	-7	4851	52
APEX II	-7	4855	62
MERCURY	-5	4988	83
STRATIX	-5	4661	79
CYCLONE	-6	4652	73

DFPMU implementation results for XILINX devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-IIE	-7	2350	45
VIRTEX	-6	2401	39
VIRTEX-E	-8	2395	48
VIRTEX-II	-5	2376	60
VIRTEX-II pro	-7	2254	73

DFPMU implementation results for LATTICE devices. The CPU features and Peripherals have been included.
Implementation	Speed Grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4E	-3	5212/711	30
ispXPGA	-4	5044/1393	39

Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com
2059 Camden Ave. Suite # 160
San Jose, CA 95124
U.S.A