ASIC

I2CM I²C Bus Interface - Master IP Core

General Description:

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CM core provides an interface between a microprocessor / microcontroller and an I2C bus. It can work as a master transmitter or master receiver depending on working mode determined by microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification including clock synchronization, arbitration, multi-master systems and High-speed transmission mode. Built-in timer allows operation from a wide range of the clk frequencies.
DI2CM is a technology independent design that can be implemented in a variety of process technologies.

Key Features:

Conforms to v.2.1 of the I2C specification
Master operation
- Master transmitter
- Master receiver
Support for all transmission speeds
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- High Speed (up to 3,4 Mb/s)
Arbitration and clock synchronization
Support for multi-master systems
Support for both 7-bit and 10-bit address-ing formats on the I2C bus

Interrupt generation
Build-in 8-bit timer for data transfers speed adjusting
Host side interface dedicated for micro-processors/microcontrollers
User-defined timing (data setup, start setup, start hold, etc.)
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

Applications:

Embedded microprocessor boards
Consumer and professional audio/video
Home and automotive radio
Low-power applications
Communication systems
Cost-effective reliable automotive systems

Units

Timer

Timer allows operation from a wide range of the input frequencies. It is programmed by an user before transmission and can be reprogrammed to change the SCL frequency.

Clock Unit

Clock Unit performs generation of the serial SCL clock. It is responsible for input spike filtering, clock synchronization and arbitration during operations in multi-master systems.

Control Logic

Control Logic manages execution of all commands sent via interface. Synchronizes internal data flow. Includes Control Register used for performing all types of I2C Bus transmissions, and Status Register indicates state of the I2C Bus and the DI2CM core.

Data Unit

It controls SDA line, performs data and address shifts during the data transmission and reception. Input data spikes are also filtered.

CPU Interface

CPU Interface performs the interface functions between DI2CM internal blocks and microprocessor. Allows easy connection of the core to a microprocessor/microcontroller system.

Licensing Options:

Single Site license option is provided to companies designing in a single site.

Multi Sites license option is provided to companies designing in multiple sites.

Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.

Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.

In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited. There is no time restriction.

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

DI2CM implementation results for ALTERA devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	290	140
ACEX1K	-1	290	130
APEX20KE	-1	290	160
APEX20KC	-7	290	185
APEX II	-7	290	210
MERCURY	-5	290	210
STRATIX	-5	290	270
CYCLONE	-5	290	250

DI2CM implementation results for XILINX devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-II	-6	150	100
SPARTAN-IIE	-7	150	109
VIRTEX	-6	150	98
VIRTEX-E	-8	150	117
VIRTEX-II	-6	150	138
VIRTEX-II pro	-7	150	136

DI2CM implementation results for LATTICE devices. The CPU features and Peripherals have been included.
Implementation	Speed Grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4E	-3	387/51	66
ispXPGA	-4	363/103	91

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