ASIC

I2CS I²C Bus Interface Slave -Base version IP Core

General Description:

I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data transmission over a short distance between many devices. The DI2CSB provides an interface between a passive target device e.g. memory, LCD display, pressure sensors etc. and an I2C bus. It can works as a slave receiver or transmitter depending on working mode determined by a master device. Very simple interface, composed with the read, write and data signals, allows easy connection to the target devices. The core doesn’t required programming and is ready to work after power up/reset. The read, write, burst read, burst write and repeated start transmissions are automatically recognized by the core. The core incorporates all features required by I2C specification. The DI2CSB supports the following transmission modes: Standard, Fast and High Speed.
DI2CS is a technology independent design that can be implemented in a variety of process technologies.

Key Features:

Conforms to v.2.1 of the I2C specification
Slave operation
- Master transmitter
- Master receiver
Supports 3 transmission speed modes
- Standard (up to 100 kb/s)
- Fast (up to 400 kb/s)
- High Speed (up to 3,4 Mb/s)
Allows operation from a wide range of input clock frequencies

Support for reads, writes, burst reads, burst writes, and repeated start
7-bit addressing
No programming required
Simple interface allows easy connection to target device e.g. memory, LCD display, pressure sensors etc.
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

Applications:

Embedded microprocessor boards
Consumer and professional audio/video
Home and automotive radio
Low-power applications
Communication systems
Cost-effective reliable automotive systems

Units

Data Unit

It controls SDA line, performs data and address shifts during the data transmission and reception. SDAI spikes are filtered by this unit.

Clock Unit

Synchronizes data and address shifts during the data transmission and reception. SCLI spikes are filtered by this unit.

Target device interface

Target device Interface performs the interface functions between DI2CSB internal blocks and target device. Allows easy connection of the core to a passive devices e.g. memory, LCD display, pressure sensors, I/O devices etc.

Control Logic

Control Logic manages execution of all commands sent via interface. Synchronizes internal data flow.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

DI2CSB implementation results for ALTERA devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	95	95
ACEX1K	-1	95	99
APEX20K	-1	95	94
APEX20KE	-1	95	130
APEX20KC	-7	95	170
APEX II	-7	95	220
MERCURY	-5	95	220
STRATIX	-5	95	230
CYCLONE	-6	95	195

DI2CSB implementation results for XILINX devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-II	-6	45	147
SPARTAN-IIE	-7	45	172
VIRTEX	-6	45	138
VIRTEX-E	-8	45	185
VIRTEX-II	-6	45	180
VIRTEX-II pro	-7	45	178

DI2CSB implementation results for LATTICE devices. The CPU features and Peripherals have been included.
Implementation	Speed Grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4E	-3	90/15	101
ispXPGA	-4	80/21	149

Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com
2059 Camden Ave. Suite # 160
San Jose, CA 95124 - USA

Units

Data Unit

Clock Unit

Target device interface

Control Logic

Licensing Options:

Comprehensible and clearly defined licensing methods without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.

Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.

- Single Design license for VHDL, Verilog source code called HDL Source - Encrypted, or plain text EDIF called Netlist - Unlimited Designs license for HDL Source or Netlist

Deliverables:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist