ASIC

INT2FP Floating Point Pipelined Converter IP Core

General Description:

The DINT2FP is the pipelined integer to floating point converter IP Core. The input and output numbers format is according to IEEE-754 standard. DINT2FP supports double word integers (4 Bytes) and single precision real numbers. Convert operation is pipelined to 3 levels. Input data are fed every clock cycle. The first result appears after latency equal to 3 clock periods and next results are available each clock cycle. Full precision and accuracy are accomplished.
DINT2FP is a technology independent design that can be implemented in a variety of process technologies.

Key Features:

Full IEEE-754 compliance
Double word integer input numbers (4 Bytes)
Single precision real output numbers
Simple interface
No programming required
3 levels pipelining

Full accuracy and precision
Results available at every clock
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready

Applications:

Math coprocessors
DSP algorithms
Embedded arithmetic coprocessor
Fast data processing & control

Units

Main FP Pipelined Unit

It performs integer to floating point conversion. Gives the complex information about the results to Result Composer module.

Argument checker

It performs input data analyze against IEEE-754 number standard compliance. The appropriate numbers and information about the input data classes are given as the results to Main FP Pipelined Unit.

Result Composer

It performs result rounding function, and data alignment to IEEE-754 standard.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email suppor

DINT2FP implementation results for ALTERA devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	609	73
APEX20K	-1	428	69
APEX20KE	-1	428	90
APEX20KC	-7	427	97
APEX II	-7	427	119
MERCURY	-5	401	140
STRATIX	-5	401	150
CYCLONE	-6	427	173
ACEX1K	-1	609	73

DINT2FP implementation results for XILINX devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-II	-6	263	74
SPARTAN-IIE	-7	244	66
PARTAN-3	-4	283	68
VIRTEX	-6	241	58
VIRTEX-E	-8	243	74
VIRTEX-II	-5	242	113
VIRTEX-II pro	-7	244	136

DINT2FP implementation results for LATTICE devices. The CPU features and Peripherals have been included.
Implementation	Speed Grade	Utilized Area [LUT/PFU]	Frequency [MHz]
ORCA4E	-3	498/75	57
ispXPGA	-4	586/162	69

Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com
2059 Camden Ave. Suite # 160
San Jose, CA 95124 - USA

Units

Main FP Pipelined Unit

Argument checker

Result Composer

Licensing Options:

Comprehensible and clearly defined licensing methods without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.

Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.

- Single Design license for VHDL, Verilog source code called HDL Source - Encrypted, or plain text EDIF called Netlist - Unlimited Designs license for HDL Source or Netlist

Deliverables:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist