DP 80390 CPU IP Core (Pipelined High Performance Microcontroller)

General Description:
DP 80390 CPU is an ultra high performance, speed optimized soft IP core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced power management unit PMU.
DP 80390CPU soft core is 100% binary-compatible with the industry standard 80390 & 8051 8-bit microcontroller. There are two configurations of DP80390CPU: Harward where internal data and program buses are separated, and von Neumann with common program and external data bus. DP80390CPU has Pipelined RISC architecture 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slowly than the original implementation for no performance penalty.
DP 80390CPU is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.

Each 80390 IP Core has built in support for DCD Hardware Debug System called DoCD^TM. It's a real-time hardware debugger provides debugging capability of a whole System on Chip (SoC).
In contrast to other on-chip debuggers DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. More details about the on Chip Debugger...

CPU Features:

100% software compatible with industry standard 80390 & 8051
- LARGE mode – 8051 instruction set
- FLAT mode – 80390 instruction set
Pipelined RISC architecture
10 times faster compared to standard 8051
24 times faster multiplication
12 times faster division
Up to 256 bytes of internal (on-chip) Data Memory
Up to 16 MB of linear Program Memory
- 64 kB of internal (on-chip) Program Memory
- 16 MB external (off-chip) Program Memory
Up to 16 MB of external (off-chip) Data Memory

User programmable Program Memory Wait States
User programmable External Data Memory Wait States
De-multiplexed Address/Data bus to allow easy memory connection
Interface for additional Special Function Registers
Fully synthesizable
Static synchronous design
Positive edge clocking and no internal tri-states
Scan test ready
2 GHz virtual clock frequency in a 0.35u technological process

Peripherals:

DoCD™ debug unit
- Processor execution control
- Read-write all processor contents
- Hardware execution breakpoints
- Three wire communication interface

Power Management Unit
- Power management mode
- Switchback feature
- Stop mode
Interrupt Controller
- 2 priority levels
- 2 external interrupt sources
- 3 interrupt sources from peripherals

Units

Control Unit

It performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks.

Opcode Decoder

Performs an instruction opcode decoding and the control functions for all other blocks.

ALU

Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.

DoCD^TM

DoCD^TM Debug Unit – it’s a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCD™ provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCD^TM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used.

Interrupt Controller

Interrupt Controller module is responsible for the interrupt manage system for the external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers.

SFRs Interface

Special Function Registers interface controls access to externally connected peripherals through SFR bus.

Program Memory Interface

Program Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader loading new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module.

External Memory Interface

External Memory Interface contains memory access related registers such as Data Page High (DPH), Data Page Low (DPL) and Data Page Pointer (DPP) registers. It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories.

Power Management Unit

Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when microcontroller is planned to use in portable and power critical applications.

Internal Data Memory Interface

Interface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.

Licensing Options:

Comprehensible and clearly defined licensing methods
without royalty fees make using the IP Core easy and simple..

Single Design license allows implementation of IP Core in single FPGA bitstream and/or ASIC design.
Unlimited Designs license, allows implementation of IP Core in unlimited number of FPGA bit-streams and ASIC designs. In all cases number of IP Core instantiations within a design, and number of manufactured chips are unlimited.
One Year license for Encrypted Netlist only

- Single Design license for VHDL, Verilog source code called
HDL Source
- Encrypted, or plain text EDIF called Netlist
- Unlimited Designs license for HDL Source or Netlist

Price:

Deliverables:

Source code:
   - VHDL Source Code or/and
   - VERILOG Source Code or/and
   - Encrypted, or plain text EDIF
VHDL & VERILOG test bench environment:
   - Active-HDL automatic simulation macros
   - ModelSim automatic simulation macros
   - Tests with reference responses
Technical documentation:
   - Installation notes
   - HDL core specification
   - Datasheet
Synthesis scripts
Example application
Technical support
   - IP Core implementation support
   - 3 months maintenance (delivery of the IP Core updates, minor and major versions changes, delivery of the documentation updates)
   - Phone & email support

DP80390CPU implementation results for ALTERA devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [LC]	Frequency [MHz]
FLEX10KE	-1	1900	57
ACEX1K	-1	1900	55
APEX20K	-1	1900	50
APEX20KE	-1	1900	63
APEX20KC	-7	1900	76
APEX II	-7	1900	74
MERCURY	-5	1900	101
STRATIX	-5	1900	98
CYCLONE	-6	1900	93

DP80390CPU implementation results for XILINX devices. The CPU features and Peripherals have been included.

Implementation	Speed Grade	Utilized Area [Slices]	Frequency [MHz]
SPARTAN-II	-6	935	58
SPARTAN-IIE	-7	935	59
VIRTEX	-6	935	51
VIRTEX-E	-8	935	59
VIRTEX-II	-6	935	107
VIRTEX II pro	-7	935	122

Tel : + 1 408 781-7778
Fax: + 1 408 268-4173
info@hitechglobal.com
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