ASIC
DP 80390XP IP Core (Pipelined High Performance Configurable Microcontroller)
General
Description:
DP80390XP is an ultra high
performance, speed optimized soft IP core of a single-chip 8-bit embedded
controller dedicated for operation with fast (typically on-chip)
and slow (off-chip) memories. The core has been designed
with a special concern about performance to power consumption ratio.
This ratio is extended by an advanced power management unit PMU.
DP80390XP soft core is 100% binary-compatible with the industry standard
8051 8-bit microcontroller. There are two configurations of DP80390XP: Harward
where internal data and program buses are separated, and von Neumann
with common program and external data bus. DP80390XP has Pipelined RISC
architecture 10 times faster compared to standard architecture and
executes 85-200 million instructions per second. This performance
can also be exploited to great advantage in low power applications
where the core can be clocked over ten times more slowly than the original
implementation for no performance penalty.
DP80390XP is delivered with fully automated testbench and complete
set of tests allowing easy package validation at each stage of SoC
design flow.
Each 80390 Core has built in support for DCD Hardware Debug System
called DoCDTM. It's a real-time
hardware debugger provides debugging capability of a whole System
on Chip (SoC).
In contrast to other on-chip debuggers DoCDTM provides non-intrusive
debugging of running application. It can halt, run, step into or
skip an instruction, read/write any contents of microcontroller including
all registers, internal, external, program memories, all SFRs including
user defined peripherals. More
details about the on Chip Debugger...
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CPU Features:
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Peripherals:
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Units
Opcode Decoder
Performs an instruction opcode decoding and the control functions for all other blocks.Control Unit
It performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks.UART0
Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register, and reading SBUF0 reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).Timers
System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 CLK periods when appropriate timer is enabled. In the counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.Compare Capture Unit
The compare/capture/reload unit is one of the most powerful peripheral units of the core. It can be used for all kinds of digital signal generation and event capturing such as pulse generation, pulse width modulation, measurements etc.Timer 2
Timer 2 – Second system timer module contains one 16-bit configurable timer: Timer 2 (TH2, TL2), capture registers (RLDH, RLDL) and Timer 2 Mode (T2MOD) register. It can work as a 16-bit timer / counter, 16-bit auto-reload timer / counter. It also supports compare capture unit if it’s presented in system. It can be used as clock source for UART0.ALU
Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.Program Memory Interface
Program Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader loading new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module.External Memory Interface
External Memory Interface contains memory access related registers such as Data Page High (DPH), Data Page Low (DPL) and Data Page Pointer (DPP) registers. It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories.DoCDTM
DoCDTM Debug Unit – it’s a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCD™ provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCDTM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used.I/O Ports
Block contains 8051’s general purpose I/O ports. Each of port’s pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3.Internal Data Memory Interface
Interface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.Extended Interrupt Controller
Interrupt Controller module is responsible for the interrupt manage system for the external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP), Extended Interrupt Enable (EIE), Extended Interrupt priority (EIP) and (TCON) registers.SFRs Interface
Special Function Registers interface controls access to externally connected peripherals through SFR bus.UART1
Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes Serial Configuration register (SCON1), serial receiver and transmitter buffer (SBUF1) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF1 loads the transmit register, and reading SBUF1 reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART1 is synchronized by Timer 1.Watchdog Timer
The watchdog timer is a 27-bit counter which is incremented every system clock periods (CLK pin). It performs system protection against software upsets.Power Management Unit
Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when microcontroller is planned to use in portable and power critical applications.Floating Point Math Unit
FPAU contains floating point arithmetic IEEE-754 compliant instructions (C float, int, long int types supported). It is used to execute single precision floating point operations such as: addition, subtraction, multiplication, division, square root, comparison absolute value of number and change of sign. Basing on specialized CORDIC algorithm a full set of trigonometric operations are also allowed: sine, cosine, tangent, arctangent. It also has built-in integer to floating point and vice versa conversion instructions. FPU supports single precision real numbers, 16-bit and 32-bit signed integers. This unit has included standard software interface allows easy usage and interfacing with user C/ASM written pro-grams.Master I2C Unit
I2C bus controller is a Master module. The core incorporates all features required by I2C specification. Supports both 7-bit and 10-bit addressing modes on the I2C bus. It works as a master transmitter and receiver. It can be programmed to operate with arbitration and clock synchronization to allow it operate in multi-master systems. Built-in timer allows operation from a wide range of the input frequencies. The timer allows to achieve any non-standard clock frequency. The I2C controller supports all transmission modes: Standard, Fast and High Speed up to 3400 kbs.Slave I2C Unit
I2C bus controller is a Slave module. The core incorporates all features required by I2C specification. It works as a slave transmitter/receiver depending on working mode determined by a master device. The I2C controller supports all transmission modes: Standard, Fast and High Speed up to 3400 kbs.SPI Unit
It’s a fully configurable master/slave Serial Peripheral Interface, which allows user to configure polarity and phase of serial clock signal SCK. It allows the microcontroller to communicate with serial peripheral devices. It is also capable of interprocessor communications in a multi-master system. A serial clock line (SCK) synchronizes shifting and sampling of the information on the two independent serial data lines. SPI data are simultaneously transmitted and received. SPI system is flexible enough to interface directly with numerous standard product peripherals from several manufacturers. Data rates as high as CLK/4. Clock control logic allows a selection of clock polarity and a choice of two fundamentally different clocking protocols to accommodate most available synchronous serial peripheral devices. When the SPI is configured as a master, software selects one of four different bit rates for the serial clock. Error-detection logic is included to support interprocessor communications. A write-collision detector indicates when an attempt is made to write data to the serial shift register while a transfer is in progress. A multiple-master mode-fault detector automatically disables SPI output drivers if more than one SPI devices simultaneously attempts to become bus master.MDU
Multiply Divide Unit – It’s a fixed point fast 16-bit and 32-bit multiplication and division unit. It provides shift and normalize operations, additionally. All operations are performed using unsigned integer numbers. The MDU contains MD0 to MD5 operands, the result registers and one control register called ARCON. This unit has included standard software interface allows easy usage and interfacing with user C/ASM written programs.
Licensing Options:Comprehensible and
clearly defined licensing methods
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Deliverables:
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 DP80390XP
implementation results for ALTERA devices. The CPU features
and Peripherals have been included. |
| Implementation | Speed Grade | Utilized Area [LC] | Frequency [MHz] |
| FLEX10KE | -1 | 4340 | 50 |
| ACEX1K | -1 | 4340 | 50 |
| APEX20K | -1 | 4340 | 45 |
| APEX20KE | -1 | 4340 | 60 |
| APEX20KC | -7 | 4340 | 70 |
| APEX II | -7 | 4340 | 72 |
| MERCURY | -5 | 4340 | 95 |
| STRATIX | -5 | 4340 | 90 |
| CYCLONE | -6 | 4340 | 85 |
 DP80390XP
implementation results for XILINX devices.
The CPU features and Peripherals have been included. |
| Implementation | Speed Grade | Utilized Area [Slices] | Frequency [MHz] |
| SPARTAN-II | -6 | 2215 | 44 |
| SPARTAN-IIE | -7 | 2215 | 45 |
| VIRTEX | -6 | 2215 | 44 |
| VIRTEX-E | -8 | 2215 | 52 |
| VIRTEX-II | -6 | 2215 | 76 |
| VIRTEX II Pro | -7 | 2215 | 90 |
| DP80390XP
implementation results for LATTICE
devices. The CPU features and Peripherals have been included. |
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| Implementation | Speed Grade | Utilized Area [LUT/PFU] | Frequency [MHz] |
| ORCA4E | -3 | 4400/1300 | 40 |
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