IEEE 802.16e (WiMAX) LDPC Encoder IP core

Error-correcting coding is an essential tool for enabling reliable communication. This Intellectual Property (IP) core provides hardware-efficient implementation of low-density parity-check (LDPC) forward error correcting (FEC) encoding schemes intended for the IEEE 802.16e. The IP core covers the entire WiMAX LDPC specification, in terms of block size and code rate. Block size and code rate can be switched on a block-by-block basis.

The decoder design is fully synchronous on a single input system clock. IP core contains input and output buffer to ease integration into user system.

Simplified Block Diagram

Main Features: 

     ► 19 code length supported
► All ratio 1/2, 2/3A, 2/3B, 3/4A, 3/4B, 5/6 supported
► On the fly change of code length and code ratio (useful for adaptive modulation and coding systems)
► Encoded throughput up to 600 Mbit/sec (Virtex-4 -12 speed grade)
► Low Latency

Simulation software

Simulation software (runs under Windows OS) delivered with this IP core implements exact fixed point model of LDPC encoder and can be used for performance simulation and test vector generation for verification.  Within simulator user can vary miscellaneous parameters of IP core (input data width, internal data width, offset min-sum parameters, maximum number of iterations) and  predict the performance of hardware realization.   Software generates text files with AWGN added to coded data and expected encoder output for efficient verification. The IP core is provided with a range of script files and a test bench to functionally simulating LDPC encoder design.

Design Features

►Technology Independent
► Fully Synchronous Design with no Latches
► Highly Modular Design with clearly defined interfaces
► Scan friendly RTL
► Consistent coding procedures

Implementation details

These implementation results are given for 5 bits input quantization and internal data width set to 8 bit

Xilinx ISE 10.1  report for 4vlx15ff676-12:

► Number of occupied Slices:          2,554 out of  6,144   (41%)
► Number of FIFO16/RAMB16s:     1 out of  48    (2%)
► Number of DSP48s:                        1 out of   32    (3%)

Altera Quartus 8.1  report for EP2S15F484C3:

► Combinational ALUTs :        2,430
► Total registers :                      1,165
► Total block memory bits :    11,960
► DSP block 9-bit elements :   2

Deliverables

     ► RTL Verilog source code or synthesized Netlist
► Full Verilog Test environment (Self checking)
► Fixed point software model  running under Windows for simulation and test patterns generation
► User guide, test specification and scripts
► Reference design
► Example Synthesis scripts
► 3 months free support to ensure successful integration into the customer’s system
► Changes to the internal design to meet customer requirements are possible

Price:

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