Advanced Encryption Standard
AES (Rijndael) IP Core
The AES encryption and
decryptionIP cores implement the AES (Rijndael) encryption standard, as
described in the NIST Federal Information Processing Standard (FIPS)
197.
The cores are designed to be highly flexible and can be integrated into
any AES design with ease. Different options are available for achieving
the best area / performance tradeoff for your requirement including a
double speed version. The cores support both encryption and
decryption functionality and can be used with all or any of the
three AES key sizes (128, 192, 256-bit). The cores are available for
licensing in both source and Netlist form.
Block Diagram: AES Standard, Mini, Tiny, and Fast
Block Diagram: Ultra Fast
| Features | Tini | Mini | Standard | Fast | Ultra Fast |
| Full compliance with the AES described in NIST FIPS 197 | YES | YES |
YES |
YES | YES |
| Speed/Throughput | Low data rate /Ultra low gate count | Medium speed / very low gate count |
Over 700 Mbps |
Fast version: up to 3 Gbps Double Speed : up to 6 Gbps |
50 Gbps |
| Simple Interface | YES | YES |
YES |
YES | YES |
| Fully synchronous design | YES | YES |
YES |
YES | YES |
| Flow-through design | YES | YES |
YES |
YES | YES |
| Data Path |
8-bit wide data path processes each round in 16 clock cycles |
16-bit wide data path processes each round in 8 clock cycles | 32-bit wide data
path processes each round in 4 clock cycles |
128-bit | 128-bit pipelined |
| Data Interface | 8-bit | 16-bit | 32-bit | 128-bit | 128-bit |
| # of Cycles required to encrypt 128-bit plain text | · 128-bit key: 176
· 192-bit key: 208 · 256-bit key: 240 |
· 128-bit key: 88
· 192-bit key: 104 · 256-bit key: 120 |
· 128-bit key:
44 · 192-bit key: 52 · 256-bit key: 60 |
· 128-bit key: 11 · 192-bit key: 13 · 256-bit key :15 |
version 1C : 1 version 2C : 2 |
| Support 128, 192 and 256-bit key sizes |
YES |
YES | YES | YES | YES |
| On-the-fly hardware key expansion |
YES |
YES | YES | YES | YES |
| No dead cycle when changing keys |
YES |
YES | YES | YES | YES |
| Key expansion in software to reduced the gate count |
YES |
YES | YES | YES | YES |
| Separate cores for encryption and decryption |
YES |
YES | YES | YES | YES |
| Combined encryption-decryption core |
YES |
YES | YES | YES | YES |
| Available solutions for more advanced modes of AES, such as AES-GCM, LRW-AES |
YES |
YES | YES | YES | YES |
| Self-checking test bench with FIPS test vectors |
YES |
YES | YES | YES | YES |
Example implementation statistics on FPGAs for the AES Standard encryption core are shown below. The throughput is calculated for the 128-bit key only.
With offline (software) key expansion
|
Xilinx Family |
Device |
Slices |
BRAM |
CLK |
I/O |
FMa (MHz) |
Throughput |
|
Virtex-4 |
XC4VLX25-11 |
98 |
3 |
1 |
110 |
219 |
637 Mbps |
|
Virtex-II Pro |
XC2VP2-7 |
93 |
3 |
1 |
110 |
253 |
736 Mbps |
|
Spartan-3 |
XC3S200-5 |
97 |
3 |
1 |
110 |
155 |
450 Mbps |
|
Spartan-3E |
XC3S250E-4 |
95 |
3 |
1 |
110 |
121 |
352 Mbps |
With hardware pre-key expansion
|
Xilinx Family |
Device |
Slices |
BRAM |
CLK |
I/O |
FMa (MHz) |
Throughput |
|
Virtex-4 |
XC4VLX25-11 |
255 |
3 |
1 |
104 |
219 |
637 Mbps |
|
Virtex-II Pro |
XC2VP2-7 |
200 |
3 |
1 |
104 |
220 |
640 Mbps |
|
Spartan-3 |
XC3S200-5 |
221 |
3 |
1 |
104 |
143 |
416 Mbps |
|
Spartan-3E |
XC3S250E-4 |
225 |
3 |
1 |
104 |
116 |
337 Mbps |
With hardware on-the-fly key expansion
|
Xilinx Family |
Device |
Slices |
BRAM |
CLK |
I/O |
FMax(MHz) |
Throughput |
|
Virtex-4 |
XC4VLX25-11 |
191 |
4 |
1 |
102 |
219 |
637 Mbps |
|
Virtex-II Pro |
XC2VP2-7 |
179 |
4 |
1 |
102 |
246 |
715 Mbps |
|
Spartan-3 |
XC3S200-5 |
184 |
4 |
1 |
102 |
124 |
360 Mbps |
|
Spartan-3E |
XC3S250E-4 |
186 |
4 |
1 |
102 |
109 |
317 Mbps |
Price:
|
|
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268-4173
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