AHB-PCI Bridge IP Core
The AHB-PCI Bridge IP Core creates a bridge between an AHB bus component and a PCI bus component.
General Architecture of AHB to PCI Bridge
Main Features:
Bridge and host-bridge mode
supported, selection through pin
CardBus and mini PCI support in both bridge and
host-bridge mode
32-bit and 33/66 MHz PCI bus interface compliant with PCI
Local Bus specification rev. 2.3
32-bit AHB master and slave interfaces, compliant with
AMBA specification rev. 2.0
AHB and PCI interfaces can run at unrelated clock
frequencies
Built-in PCI arbiter can control up to 7 PCI agents
DMA can generate all existing PCI commands with burst
transfers up to 224 data
DMA require no CPU processing time once initiated
PCI master devices can directly transfer data to/from AHB
devices
AHB master devices can directly transfer data to/from PCI
devices
PCI master transfers do not consume CPU processing time
Concurrent DMA read, DMA write, AHB-to-PCI and PCI-to-AHB
transfers
C-language software design kit.
Example PCI plug-n-play "BIOS" code
Available in VHDL and Verliog
Target
Technologies:
- ASIC .35u and below
- Structured ASIC and other masked ICs:
- FPGA with embedded processor stripe such as: Altera Excalibur-ARM
Deliverables:
- Standard VHDL/Verilog source code for ASIC design and
simulation.
- Highly optimized encrypted VHDL code for FPGAs
- C-language software design kit.
- Sample PCI plug and play code for easy software development.
Price:
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HiTech Global Design & Distribution,
LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124
Tel: +1 408 781-8043
Fax: +1 408 268-4173
info@HiTechGlobal.com