SPDIF-AES/EBU to I2S Converter IP Core
Overview:
The CWda03 is a digital
audio receiver IP core implementing the SPDIF, AES/EBU, AES3 or IEC60958
standards. The CWda03 inputs an SPDIF signal and samples it with a fast
clock to extract the clock, audio and control data from it. It outputs
PCM audio data in the well known I2S format, popular in many data
converters.
Functional
Description:
Glitch Filter & Digital Data and Clock Recovery: filters
glitches due to slow transitions in the SPDIF-AES/EBU signal; clock and
data recovery based on fast sampling and edge detection.
SPDIF-AES/EBU Decoder: decodes the SPDIF-AES/EBU
signal according to the IEC60958, AES3 or AES/EBU standards.
I2S Output FIFO: converts LSB-first serial data to the MSB-first I2S format. When mode=0, an external PLL circuit must be used to filter the jitter out of the recovered clock. The jitter-free clock is used to retrieve the data signal from a shallow output FIFO. When mode=1, the PLL circuit is not necessary, but the output data contains jitter.
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Key Features: • Supports the following standards: IEC60598 (SPDIF), AES3, AES/EBU Completely digital receiver. No need to use input PLL for synchronization. Applications: |
Deliverables:
Part Number: CWda03 Price:
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Implementation Results:
Other Digital Audio IP Cores:
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