I2S to SPDIF-AES/EBU Converter IP Core

I2S to SPDIF-AES/EBU Converter IP Core

Overview:

The CWda04 is a digital audio transmitter IP core implementing the SPDIF, AES/EBU, AES3 or IEC60958 standards. The CWda04 inputs the well known I2S format, popular in many data converters. It also allows customizing the SPDIF-AES/EBU control bits according to user applications.

Functional Description:
I2S Receiver: Reads the incoming I2S signal and generates the appropriate addresses to store the data into the buffers implemented in the Ping-pong buffers module. This module uses the sclk (64x the sampling frequency) as its single clock signal.

Ping-pong Buffers: The ping-pong buffers are able to store 2 sub-frames: one buffer stores the incoming sub-frame, while the other buffer transmits the previously stored sub-frame. This module is also responsible for the conversion from the MSB-first to LSB–first representation.

SPDIF Transmitter: This module generates the SPDIF-AES/EBU signal. The mclk signal (256x the sampling frequency) is used for this purpose. The SPDIF Transmitter module generates the appropriate preambles and encodes the data according to the Biphase Mark Code (BMC) format.

Key Features:

• Supports the IEC60598 (SPDIF, AES3, AES/EBU) and I2S standards
• Supports sample rates up to frequency mclk/256 (384KHz for mclk = 98MHz)
• Supports up to 24 bits per sample
• User defined SPDIF-AES/EBU control bits can be inserted in the SPDIF-AES/EBU signal
• Low power mode when idle

Applications:

Digital audio (CD, SACD, DVD-Audio), or multimedia systems. (VCD, SVCD, DVD, etc.).

Deliverables:

Detailed datasheet and user documentation for system integration.
HDL Testbench covering all functionalities of the core and including automatic verification of the correctness of the responses.
Options:
o FPGA Netlist
o HDL (VHDL or Verilog) source code.
o Simulation script.
o Synthesis and/or place and route scripts.
o Prototyping boards.

Part Number: CWda04

Price:

How To Purchase

Implementation Results:

Family	Example Device	Fmax (MHz)	Slices	IOB	GCLK	BRAM	Design Tools
Spartan-3	XC3S50-4	161	47	18	2	0	ISE 6.3.03i
Spartan-IIE	XC2S50E-6	111	44	16	2	0	ISE 6.3.03i
Virtex-II Pro	XC2VP2-5	207	42	18	2	0	ISE 6.3.03i
Virtex-II	XC2V40-4	207	42	18	2	0	ISE 6.3.03i
Virtex-4	XC4Vfx12-10	201	45	18	2	0	ISE 6.3.03i

Technology	Resources	Frequency (fClk)
UMC 180 nm	1,450 Gates	950 MHz

Other Digital Audio IP Cores:

IP Name/Part #	Description
CWda03	SPDIF-AES/EBU to I2S Converter
CWda04	I2S to SPDIF-AES/EBU Converter
SPDIF-CWda14	Configurable SPDIF-AES/EBU Receiver
SPDIF-CWda15	Configurable SPDIF-AES/EBU Transmitter
I2S-CWda16	Configurable Digital Audio Serial Input
I2S-CWda17	Configurable Digital Audio Serial Output
SDI-CWda41	SDI Audio De-embedder
SDI-CWda42	SDI Audio Embedder
CWda30	3rd Order Stereo Digital Audio Sigma-Delta Modulator
SRC-CWda50	Stereo / Mono Sample Rate Converter
SRC-CWda52	Multi-Channel Audio Sample Rate Converter (ASRC)

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