DDR SDRAM Controller IP Core
Overview:
The Double Data Rate (DDR) SDRAM
Controller Core is designed for use in applications requiring high
memory throughput, high clock rates and full programmability.
The core accepts commands using a simple local interface and translates
them to the command sequences required by DDR SDRAM devices. The core
also performs all initialization and refresh functions.
The core uses bank management techniques to monitor the status of each
SDRAM bank. Banks are only opened or closed when necessary, minimizing
access delays. Up to eight banks can be managed at one time. A command
queuing interface is used enabling multiple, random address requests to
be queued up, each with lengths as short as 2 DDR data cycles. This
architecture provides optimal bandwidth utilization both for cases of
short transfers to highly random address locations as well as cases of
longer transfers to contiguous address space.
The core is provided with run-time programmable inputs for all timing
parameters (tCL, tRC, tRCD, tRP, tMRD, tRRD, tRFC, tRAS) as well as
memory configuration and refresh period settings. This ensures
compatibility with all DDR SDRAM configurations.
Three optional add-on modules are available:
-
Error Correction Coding (ECC) Module - Provides single bit correction and double bit detection
-
Read-Modify-Write Module (RMW) - Enables partial word writes when using ECC
-
Multi-Burst Module - Enables long burst length requests and handles address alignment for requests not aligned to the
boundaries of the programmed burst length
DDR SDRAM Controller IP Core Features:
- Command queuing and bank management enable up to 100% memory throughput
- Supports auto-precharge commands for optimum random access performance
- Achieves high clock rates with minimal routing constraints
- Supports all standard DDR SDRAM chips and DIMMs
- Run-time configurable timing parameters and memory settings
- A variety of read capture options are supported
- Automatic generation of initialization and refresh sequences
- ECC, RMW and Multi-Burst add-on modules available
- Supports self-refresh and power down modes
- Source code available
- Customization and Integration services available
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Data Rate (Per Pin) | Clock Rate | Size |
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|
| Virtex-4 | 400 Mbit/s | 200 MHz | 920 Slices | ||
| Spartan-3 | 267Mbit/s | 133 MHz | 920 Slices | ||
| Virtex-II Pro | 333 Mbit/s | 167 MHz | 920 Slices | ||
| Virtex-II | 333 Mbit/s | 167 MHz | 920 Slices | ||
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Data Rate (Per Pin) | Clock Rate | Size | ||
| Cyclone II | 333 Mbit/s | 167 MHz | 1,950 LEs | ||
| Stratix II | 400 Mbit/s | 200 MHz | 1,950 LEs | ||
| Stratix | 400 Mbit/s | 200 MHz | 1,950 LEs | Xilinx Virtex-II Pro DDR Evaluation Board | |
| Cyclon | 267 Mbits/s | 133 MHz | 1,950 |
|
|
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Data Rate (Per Pin) | Clock Rate | Size | ||
| XP | 333 Mbit/s | 167 MHz | 920 Slices | ||
| ECP | 400 Mbit/s | 200 MHz | 920 Slices | ||
| EC | 400 Mbit/s | 200 MHz | 920 Slices | ||
| Device | Data Rate (Per Pin) | Clock Rate | Size | ||
| ASIC | >800 Mbit/s | >400 MHz | 13,700 Gates |
IP Core Deliverables:
· Core (Netlist or Source Code)
· Comprehensive Verification Suite (Source Code)
· Complete Documentation
· Expert Technical Support & Maintenance Updates
Price:
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Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com
2059 Camden Ave. Suite # 160
San Jose, CA 95124
U.S.A