8051 IP Core (Pipelined High Performance Microcontroller) 

8051 IP Core General Description:
DP 8051 is an ultra high performance, speed optimized soft IP core of a single-chip 8-bit embedded controller dedicated for operation with fast (typically on-chip) and slow (off-chip) memories. The core has been designed with a special concern about performance to power consumption ratio. This ratio is extended by an advanced Power Management Unit (PMU).

The 8051 soft IP core is 100% binary-compatible with the industry standard 8051 8-bit microcontroller. There are two configurations of the  8051 IP core: Harvard where internal data and program buses are separated, and Von Neumann with common program and external data bus. DP 8051 IP core has Pipelined RISC architecture 10 times faster compared to standard architecture and executes 85-200 million instructions per second. This performance can also be exploited to great advantage in low power applications where the core can be clocked over ten times more slowly than the original implementation for no performance penalty.

The 8051 IP core is delivered with fully automated testbench and complete set of tests allowing easy package validation at each stage of SoC design flow.

Each  8051 IP core has built in support for Hardware Debug System called DoCD^TM. It's a real-time hardware debugger provides debugging capability of a whole System on Chip (SoC).

In contrast to other on-chip debuggers DoCD^TM provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. More details about the on Chip Debugger...

8051 IP Core Block Diagram

Control Unit
It performs the core synchronization and data flow control. This module is directly connected to Opcode Decoder and manages execution of all microcontroller tasks.

Opcode Decoder
Performs an instruction opcode decoding and the control functions for all other blocks.

Timers
System timers module. Contains two 16 bits configurable timers: Timer 0 (TH0, TL0), Timer 1 (TH1, TL1) and Timers Mode (TMOD) registers. In the timer mode, timer registers are incremented every 12 CLK periods when appropriate timer is enabled. In the counter mode the timer registers are incremented every falling transition on their corresponding input pins (T0, T1), if gates are opened (GATE0, GATE1). T0, T1 input pins are sampled every CLK period. It can be used as clock source for UARTs.

UART0
Universal Asynchronous Receiver & Transmitter module is full duplex, meaning it can transmit and receive concurrently. Includes Serial Configuration register (SCON), serial receiver and transmitter buffer (SBUF) registers. Its receiver is double-buffered, meaning it can commence reception of a second byte before a previously received byte has been read from the receive register. Writing to SBUF0 loads the transmit register, and reading SBUF0 reads a physically separate receive register. Works in 3 asynchronous and 1 synchronous modes. UART0 can be synchronized by Timer 1 or Timer 2 (if present in system).

ALU
Arithmetic Logic Unit performs the arithmetic and logic operations during execution of an instruction. It contains accumulator (ACC), Program Status Word (PSW), (B) registers and related logic like arithmetic unit, logic unit, multiplier and divider.

DoCD^TM
DoCD^TM Debug Unit – it’s a real-time hardware debugger provides debugging capability of a whole SoC system. In contrast to other on-chip debuggers DoCD™ provides non-intrusive debugging of running application. It can halt, run, step into or skip an instruction, read/write any contents of microcontroller including all registers, internal, external, program memories, all SFRs including user defined peripherals. Hardware breakpoints can be set and controlled on program memory, internal and external data memories, as well as on SFRs. Hardware breakpoint is executed if any write/read occurred at particular address with certain data pattern or without pattern. The DoCD^TM system includes three-wire interface and complete set of tools to communicate and work with core in real time debugging. It is built as scalable unit and some features can be turned off to save silicon and reduce power consumption. A special care on power consumption has been taken, and when debugger is not used it is automatically switched in power save mode. Finally whole debugger is turned off when debug option is no longer used.

I/O Ports
Block contains 8051’s general purpose I/O ports. Each of port’s pin can be read/write as a single bit or as a 8-bit bus P0, P1, P2, P3.

Internal Data Memory Interface
Interface controls access into the internal memory of size up to 256 bytes. It contains 8-bit Stack Pointer (SP) register and related logic.

Interrupt Controller
Interrupt Controller module is responsible for the interrupt manage system for the external and internal interrupt sources. It contains interrupt related registers such as Interrupt Enable (IE), Interrupt Priority (IP) and (TCON) registers.

SFRs Interface
Special Function Registers interface controls access to externally connected peripherals through SFR bus.

Program Memory Interface
Program Memory Interface contains Program Counter (PC) and related logic. It performs the instructions code fetching. Program Memory can be also written. This feature allows usage of a small boot loader loading new program into ROM, RAM, EPROM or FLASH EEPROM storage via UART, SPI, I2C or DoCD™ module.

External Memory Interface
External Memory Interface contains memory access related registers such as Data Page High (DPH), Data Page Low (DPL) and Data Page Pointer (DPP) registers. It performs the external Program and Data Memory addressing and data transfers. Program fetch cycle length can be programmed by user. This feature is called Program Memory Wait States, and allows core to work with different speed program memories.

Power Management Unit
Power Management Unit contains advanced power saving mechanisms with switchback feature, allowing external clock control logic to stop clocking (Stop mode) or run core in lower clock frequency (Power Management Mode) to significantly reduce power consumption. Switchback feature allows UARTs, and interrupts to be processed in full speed mode if enabled. It is very desired when microcontroller is planned to use in portable and power critical applications.

DP 8051 IP core implementation results for ALTERA devices. The CPU features and Peripherals have been included. Implementation Speed Grade Utilized Area [LC] Frequency [MHz] FLEX10KE -1 2250 57 ACEX1K -1 2250 57 APEX20K -1 2250 50 APEX20KE -1 2250 63 APEX20KC -7 2250 74 APEX II -7 2250 76 MERCURY -5 2250 100 STRATIX -5 2250 96 CYCLONE -6 2250 91 CYCLONE II -6 2250 93

DP 8051 IP core implementation results for XILINX devices. The CPU features and Peripherals have been included.

Implementation Speed Grade Utilized Area [Slices] Frequency [MHz] SPARTAN-II -6 1100 61 SPARTAN-IIE -7 1100 63 VIRTEX -6 1100 58 VIRTEX-E -8 1100 67 VIRTEX-II -6 1100 103 VIRTEX II pro -7 1100 116 Virtex-4 -11 1100 107 DP 8051 IP core implementation results for LATTICE devices. The CPU features and Peripherals have been included. Implementation Speed Grade Utilized Area [LUT/PFU] Frequency [MHz] EC -5 2224/490 67 ECP -5 2146/490 73 XP -5 2224/490 61

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