LEON 3 SPARC V8 Processor IP Core


The LEON3 is a synthesizable VHDL model of a 32-bit processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL license, allowing free and unlimited use for research and education. LEON3 is also available under a low-cost commercial license, allowing it to be used in any commercial application to a fraction of the cost of comparable IP cores.

The LEON3 processor has the following features:
  • SPARC V8 instruction set with V8e extensions
  • Advanced 7-stage pipeline
  • Hardware multiply, divide and MAC units
  • High-performance, fully pipelined IEEE-754 FPU
  • Separate instruction and data cache (Harvard architecture) with snooping
  • Configurable caches: 1 - 4 sets, 1 - 256 kbytes/set. Random, LRR or LRU replacement
  • SPARC Reference MMU (SRMMU) with configurable TLB
  • AMBA-2.0 AHB bus interface
  • Advanced on-chip debug support with instruction and data trace buffer
  • Multi-processor support (SMP)
  • Power-down mode
  • Robust and fully synchronous single-edge clock design
  • Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
  • Fault-tolerant  and SEU-proof version available for space applications
  • Extensively configurable
  • Large range of software tools: compilers, kernels, simulators and debug monitors

The LEON3 processor is distributed as part of the GRLIB IP library, allowing simple integration into complex SOC designs. GRLIB also includes a configurable LEON3 multi-processor design, with up to 4 CPU's  and a large range of on-chip peripheral blocks.


The model comes with a generic testbench, and can be simulated by Modelsim, Ncsim and GHDL simulators. It also features a built-in disassembler for debug purposes.


The LEON3 processor can be synthesised with common synthesis tools such as Synplify, Synopsys DC and Cadence RC. The core will reach up 125 MHz on FPGA and 400 MHz on 0.13 um ASIC technologies. The core area (pipeline, cache controllers and mul/div units) requires only 20 - 25 Kgates or 3500 LUT, depending on the configuration. The LEON3 processor can also be synthezised with Xilinx XST and Altera Quartus, either through scripts or by using the graphical interfaces of the Xilinx and Altera tools.


The LEON3 processor is fully prametrizable through the use of VHDL generics, and does not rely on any global configuration package. It is thus possible to instantiate several processor cores in the same design with different configurations. The LEON3 template designs can be configured using a graphical tool built on tkconfig from the linux kernel. This allows new users to quickly define a suitable custom configuration. The configuration tool not only configures the processor, but also other on-chip peripherals such as memory controllers and network interfaces.

LEON3 is distributed as part of the GRLIB IP library, and the library contains LEON3 templates designs for several popular FPGA prototyping boards. Pre-synthesized FPGA programming files are also provided.

SPARC V8 compliance

LEON3 has been certified by SPARC International as being SPARC V8 conformant. The certification was completed on May 5, 2005.

Software Development

Being SPARC V8 conformant, compilers and kernels for SPARC V8 can be used with LEON3 (kernels will need a LEON bsp). To simplify software development, Gaisler Research is providing BCC, a free C/C++ cross-compiler system based on gcc and the Newlib embedded C-library. BCC includes a small run-time with interrupt support, but does not support tasking. For multi-threaded and/or multi-processor applications, a LEON3 port of the eCos real-time kernel is available. A LEON3 port of RTEMS 4.6.1 is available in form of the RCC cross-compiler, a system that supports RTEMS for ERC32, LEON2 and LEON3.

LINUX support for LEON3 is provided through a special version of the SnapGear Embedded Linux distribution. SnapGear Linux is a full source package, containing kernel, libraries and application code for rapid development of embedded Linux systems. The LEON3 port of SnapGear supports both MMU and non-MMU LEON configurations, as well as the optional V8 mul/div instructions and floating-point unit (FPU). A single cross-compilation tool-chain is provided which is capable of compiling the kernel and applications for any configuration.

Debugging is generally done using the gdb debugger, and a graphical front-end such as DDD or Eclipse. It is possible to perform source-level symbolic debugging, either on a simulator or using real target hardware. Gaisler Research provides TSIM, a high-performance LEON3 simulator which seamlessly can be attached to gdb and emulate a LEON3 system at more than 10 MIPS. The GRMON monitor interfaces to the LEON3 on-chip debug support unit (DSU), implementing a large range of debug functions as well as a GDB gateway.

* SPARC is a registered trademark of SPARC International.

Evaluation Boards:
GR-PCI-XC2V PCI Xilinx Virtex II Development Board GR-3S1500 Xilinx Spartan 3  Leon Development Board

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