Implemented in more than 100 ASIC and FPGA DesignsPCI-SIG Certified PCI Express IP Core
Overview:
The PCI Express IP Core is compliant with the PCI Express Base Specification Revision 1.1, and implements all three layers of the
PCI Express specification (Transaction, Data Link, and Physical)
General Features:
● x8 PCI Express
IP Core
● 64-bit data path at 2.5
Gbps per lane
● x1 Core (125 MHz),
x4 Core (125 MHz), x4 Core (250 MHz), or x8 Core (250 MHz)
and 125 MHz or 250 MHz frequency for 20 Gbps full-duplex bandwidth
● Suitable for Root
Complex, Endpoint, and Dual Mode / Shared Silicon
● PCI Express Base
Specification 1.1 compliant
● Up to eight Virtual
Channels (VCs)
● Receive and Retry buffer
size configurable
● Intel’s PIPE interface
(8-bit or 16-bit mode) to interface between the PHY MAC and PHY physical
coding sub-layer (PCS) /Physical Media Attachment (PMA) layers
● Receive/transmit user
Application Interface
● Input test port for
enabling/disabling specific modes (remote boot, error generation...)
● Output test port for
monitoring (errors, state machine, flow control...)
● Fully compliant PHY PCS
sub-layer (125 MHz or 250 MHz)
- 1-bit PCS/PMA for FPGA
Altera Stratix GX
Altera Stratix GXII
Xilinx Virtex-4 FX
- Wrapper for external PHY
PXPIPE for Philips PX1012A (x1)
Wrapper for Genesys GL9714
(x4 or x8)
Wrapper for PMC Sierra PM8358 (x8)
Wrapper for TI xIO1100 (x1)
|
Customization The Core can be customized with a provided wizard that permits modification of the following parameters: ● Type of Core: Root Port, Endpoint, Switch (upstream port), Switch (downstream port), Bridge port, inverse Bridge port, or dual mode / shared silicon ● Maximum Payload Size (Max_Payload_Size): up to 4 KB ● Number of lanes: 1 to 4 (125 MHz) and 1 to 8 (250 MHz) ● Number of Virtual Channels (VCs): 1 to 8 (the unimplemented VCs do not get synthesized with the Core.) ● Receive Buffer configuration ● Dedicated blocks of DPRAM per initialized VC ● One common block of DPRAM for all initialized VCs ● Buffer sizes: ● Receive Buffer size: per VC ● Retry Buffer size ● BAR definition for Type 0 Configuration Spaces ● Memory windows for Type 1 Configuration spaces ● Plug-and-Play parameters Data Transfer ● Supports up to 4KB data payload transfer ● Supports all Memory, I/O, Configuration, and Message transactions ● Highly optimized Application interface for maximum effective throughput Configuration ● Implements Type 0 Configuration space for Endpoint designs ● Implements Type 1 Configuration space for Root Complex, Switch, and Bridge designs ● Up to 6 BARs plus expansion ROM can be implemented for Endpoints ● All I/O and memory windows implemented for Root complex, Switch, and Bridge components Power Management and Interrupt ● All Power State and associated logic implemented ● Legacy PCI Power Management support ● Native Active State Power Management L0s state support ● Power Management Event (PME message) and Beacon (Wake-Up) support ● MSI (up to 32, mapped to any TC) and INT message support ● Controlled easily by Application signals Reference Design ● Master/target Application interface type for Endpoint and Root Complex designs ● Target connected to SRAM and registers ● Highly pipelined Master interface connected to SRAM module and data generator ● Provided as source code for free adaptation to user’s design Design Files ● Standard VHDL and Verilog source code for ASIC design |
|
|
PCI Express External PHY
PCI Express External PHY |
Free Evaluation: The Evaluation package provides Core functionality similar to the purchased product but some features may be disabled and the evaluation will stop functioning after a certain time. Please contact us for registration
Price:
|
|
HiTech Global Design & Distribution, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124 USA
Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com