PCI-X IP Core (ASIC & FPGA)
Overview:
The PCIX PCI IP core provides an integrated solution for interfacing any user application or system to 32bit and 64bit PCI peripheral devices. The core is programmable and customizable; almost all features can be enabled/disabled to suit specific needs and the core can be adapted to run in any PCI environment. This core is well suited for programmable logic designs but can also be implemented in ASIC designs.
The PCIX core is built around a target and a master state machine that control all operations and insure coherency and synchronization with PCI bus operations. Data transfer is operated by a 32bit/ 64bit bidirectional registered data path as shown below.
Features:
General
• 32-bit/64-bit PCI-X & PCI master/target interface
• Supports bus speed up to 133 MHz
• Multi-function core can implement up to 2 independent functions
• Full support for 64-bit addressing
• PCI-X Specification 2.0a mode 1 compliant
• PCI Specification 3.0 compliant
• Supports PCI power management
• Built-in support for in-site programming through JTAG interface
• Supports Message Signalled Interrupts
Customization
• Easy customization with the PCI Wizard's user interface and on-line
help.
• PCI Wizard has built-in support for VHDL and Verilog.
• All features can be parameterized, removing all unused logic
• Full plug-and-play support
Configuration
• Supports all required and optional type 0 configuration registers
• Up to 6 BARs plus expansion ROM can be implemented
• Up to 32 user defined configuration registers
Data Transfer
• Supports up to 4KB burst transfers with zero wait-state insertion.
• Supports all memory and I/O commands
• Supports interrupt acknowledge cycles in target mode
• Can insert wait-states and generate all types of terminations
• Up to two split channels and 32 outstanding split transactions
DMA
• Up to 4 independent DMA channels with rotating priority
• Flexible backend interface can directly control FIFO devices.
• Can generate all existing bus commands
• Optional scatter-gather support
• 64-bits data transactions are dynamically negotiated
• Split is fully supported on all DMA channels
Design Files
• Standard VHDL and Verilog source code for ASIC design and simulation
• Highly optimized encrypted VHDL code for Altera & Xilinx FPGAs
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Deliverables:
• Configurable IP controller
• Customization wizard
• Synthesis files (VHDL & Verilog RTL)
• Simulation models (VHDL & Verilog RTL)
• Reference Design
• Bus Functional Model (BFM)
• Software Development Kit (SDK)
• Complete technical documentation
• Technical support and maintenance provided directly by the design team
Price:
PCI-X Evaluation Boards
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| Altera Stratix-II | Altera Stratix | Xilinx Virtex-5 |
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HiTech Global Design & Distribution
2059 Camden Ave. Suite # 160
San Jose, CA 95124
U.S.A
Tel : + 1 408 781-8043
Fax: + 1 408 268-4173
info@hitechglobal.com