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Serial ATA (SATA) I/II/III Host IP Core (FPGA & ASIC)

Compliance certified by the UNH labs, the Serial ATA Host Controller IP Core provides an interface to high speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding.

SATA IP Core Main Features: 

►Compliance Certified by UNH Labs
10/20/40 bit PHY interface
Includes GTX based PHY with OOB, Speed Negotiation and clock generation OR external SAPIS compliant PHY interface
Supports SATA Gen 1 (1.5 Gbps), Gen 2 (3.0 Gbps) and Gen 3 (6.0 Gbps)
AXI, WISHBONE, OPB, PLB or AHB slave interface
AXI and direct FIFO Streaming Interface
Configurable depth data FIFO
Implements the shadow register block and the serial ATA status and control registers
Parallel ATA legacy software compatibility
48-bit address feature set supported
8b/10b coding and decoding
Automatic throttling by inserting and observing HOLD primitives
CONT and data scramblers to reduce EMI
CRC generation and checking
Power management support (partial and slumber)
Optional native mode programming model
Many configuration options

Serial ATA (SATA) IP Core Architecture:

The Serial ATA (SATA) Link and Transport Layer Core implements a serial ATA host interface which connects to a SATA PHY via a 10/20/40 bit interface and provides a Wishbone slave interface for register and DMA access. It consists of the link layer module -with 10bit data paths to the physical layer -and a transport layer module which connects to the system via a 
Wishbone slave interface.

SAPIS PHY Interface:
This interface connects to any SAPIS compliant serial ATA Phy. Power management and speed negotiation signals are included. The Phy interface is synchronous to the Phy clock domain, which may have a different clock frequency than the system clock domain. Synchronization is done by the Serial ATA Link and Transport Layer Core. 

Wishbone Slave Interface:
The slave interface is used to access all core internal registers as well as the data FIFO. Software or an external DMA unit can write transmit data into the data FIFO or can read from the FIFO. This interface can be easily adapted to AMBA AHB bus interface with our WISHBONE/AMBA bridge. 

DMA Handshake:
Simple handshake signals are provided to connect a DMA unit to the core module. The DMA requests will be asserted as soon as any transmit data is available or is needed in the core's data FIFO. The DMA unit will then access the data FIFO via the Wishbone slave interface. A system interrupt will inform host software on completion of a data transfer. 
Automatic flow control mechanisms control data throttling to avoid underflow or overflow of the transmit data FIFO. The DMA unit (or host software) may work at any speed without the risk of data loss. Data FIFO thresholds can be adjusted to optimize the data flow control. 

Size & Speed:
Sample Synthesis results for SATA Host IP Core. The goal was smallest and fastest implementation.

Family

Example Device

Fmax (MHz)

Slices 1

IOB

GCLK

BRAM

MULT/ DSP48

DCM / CMT

MGT

PPC

Design Tools

Spartan-6

XC6SLX45T-2

>100

880

4

3

1

0

1

1

0

ISE 13.2

Virtex-5

XC5VFX70T-1

>135

1169

4

3

1

0

1

1

0

ISE 13.2

Virtex-6

XC6VLX240T-1

>135

834

4

3

1

0

1

1

0

ISE 13.2

Kintex-7

XC7K325T-1

>180

776

4

3

1

0

1

1

0

ISE 14.1

Virtex-7

XC7VX485T-2

> 180

849

4

3

1

0

1

1

0

ISE 14.1

Zynq

XC7Z045-2

> 190

774

4

3

1

0

1

1

0

ISE 14.1