Serial ATA (SATA) Host IP Core (FPGA & ASIC)
The Serial ATA (SATA) Link and Transport Layer IP core provides an interface to high-speed serial link replacements for the parallel ATA attachment of mass storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit technology and 8b/10b encoding. This core is fully compliant to the Serial ATA 1.0a specification and provides some features of the Serial ATA (SATA) II extensions.SATA IP Core Main Features:
- 10 bit PHY interface
- Connects to SAPIS compliant serial ATA (SATA) PHY
- Fully compliant to SATA Gen 1 (1.2 Gb/s) and Gen 2 (2.4 Gb/s)
- Wishbone (Coreconnect, AMBA) slave interface for register access and FIFO/DMA data transfers
- Only very few FF's in the PHY clock domain, main part on the Wishbone clock
- 128 byte (32 double word) data FIFO (optional 256 byte)
- Implements the shadow register block and the serial ATA (SATA) status and control registers
- Parallel ATA legacy software compatibility
- 48-bit address feature set supported
- Master only emulation (supports 1 device)
- 8b/10b coding and decoding
- CONT and data scramblers to reduce EMI
- CRC generation and checking
- Auto inserted HOLD primitives
- Power management support (partial and slumber)
- Optional native mode programming model
- Many configuration options
Serial ATA (SATA) IP Core Architecture:
The Serial ATA (SATA) Link and Transport Layer Core implements a serial ATA host interface which
connects to a SATA PHY via a 10bit interface and provides a Wishbone slave interface for register
and DMA access. It consists of the link layer module -with 10bit data paths to the physical layer -and a transport
layer module which connects to the system via a
Wishbone slave interface.
SAPIS PHY Interface:
This interface connects to any SAPIS compliant serial ATA Phy. Power management and speed
negotiation signals are included. The Phy interface is synchronous to the Phy clock
domain, which may have a different clock frequency than the system clock domain.
Synchronization is done by the Serial ATA Link and Transport Layer Core.
Wishbone Slave Interface:
The slave interface is used to access all core internal registers as well as the data FIFO. Software or an external DMA unit can write
transmit data into the data FIFO or can read from the FIFO. This interface can be easily adapted to AMBA
AHB bus interface with our WISHBONE/AMBA bridge.
DMA Handshake:
Simple handshake signals are provided to connect a DMA unit to the core module. The
DMA requests will be asserted as soon as any transmit data is available or is needed in the
core's data FIFO. The DMA unit will then access the data FIFO via the Wishbone slave interface.
A system interrupt will inform host software on completion of a data transfer.
Automatic flow control mechanisms control data throttling to avoid underflow or overflow of the transmit data FIFO. The DMA unit (or host software) may work at any speed without the risk of data loss. Data FIFO thresholds can be
adjusted to optimize the data flow control.
Size & Speed:
Sample Synthesis results for SATA Host IP Core. The goal was smallest and fastest implementation.
| Technology | Gate Count | Fmax |
| UMC 0.18 um | 24,000 gates | Up to 300MHz PHY clock up to 200 MHz system clock |
| Xilinx Virtex-5(XC5VLX50T) | 861 Slices | 100 MHz |
Price:
Reference Boards:
HiTech Global
Virtex-5
PCI Express/SATA Development Board
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HiTech Global Design & Distribution, LLC
2059 Camden Ave. Suite # 160
San Jose, CA 95124
Tel:+ 1 408 781-8043
Fax: + 1 408
268-4173
Email:
info@hitechglobal.com