12-bit ADC (10.25 GSPS) / Dual 16-bit DAC (12.6 GSPS) FMC+ Module

Product Updates

Single 12-bit ADC (10.25 GSPS)/ Dual 16-bit DAC (12.6 GSPS) FMC+ Module (Vita57.4)

This Vita57.4/ JESD204B compliant FMC+ module is powered by Analog Devices' AD9213 (12-bit ADC @ 10.25GSPS), AD9172( dual 16-bit DAC @ 12.6 GSPS), and HMC7044 attenuator. The main interface with a host FPGA is supported through 16 serial transceivers.

The AD9213 is a single 12-bit, 10.25 GSPS, RF analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 has been optimized to support high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low code error rates (CER). The AD9213 features a 16-lane JESD204B interface to support its maximum bandwidth capability.

ADC (AD9213) Parameters

High instantaneous dynamic range

Noise spectral density 154dBFS/Hz
SFDR 68dBc (1GHz, −1dBFS)

Low power consumption: 5.1W at 10Gsps

Integrated Input Buffer (6.5GHz input bandwidth)

1.4V p-p full-scale input with RIN=50 Ω
Overvoltage protection

16-lane JESD204B output (up to 16 Gbps line rate)

Multichip sync capable with 1 sample accuracy

DDC NCO synchronization included

Fast overrange detection for efficient AGC

Integrated DDC

Selectable decimation factors
16-profile settings for fast frequency hopping

On-chip temperature sensor

On-chip negative voltage generators

Low CER <1e−16

Applications:

Spectrum analyzers
Military communications
Radar
High performance digital storage oscilloscopes
Active jamming/antijamming
Electronic surveillance and countermeasures
DPD observation path

DAC (AD9172) Parameters

Supports multiband wireless applications
- 3 bypassable, complex data input channels per RF DAC
- 1.54 GSPS maximum complex input data rate per input channel
- 1 independent NCO per input channel
Proprietary, low spurious and distortion design
- 2-tone intermodulation distortion (IMD) = −83 dBc at 1.8 GHz, −7 dBFS/tone RF output
- Spurious free dynamic range (SFDR) <−80 dBc at 1.8 GHz, −7 dBFS RF output
Flexible 8-lane, 15.4 Gbps JESD204B interface
- Supports single-band and multiband use cases
- Supports 12-bit high density mode for increased data throughput
Multiple chip synchronization
- Supports JESD204B Subclass 1
Selectable interpolation filter for a complete set of input data rates
- 1×, 2×, 3×, 4×, 6×, and 8× configurable data channel interpolation
- 1×, 2×, 4×, 6×, 8×, and 12× configurable final interpolation
Final 48-bit NCO that operates at the DAC rate to support frequency synthesis up to 6 GHz
Transmit enable function allows extra power saving and downstream circuitry protection
High performance, low noise PLL clock multiplier
- Supports 12.6 GSPS DAC update rate
- Observation ADC clock driver with selectable divide ratios
Low power
- 2.55 W at 12 GSPS, dual channel mode

Applications:

Wireless communications infrastructure
- Multiband base station radios
- Microwave/E-band backhaul systems
Instrumentation, automatic test equipment (ATE)
Radars and jammers