AD9082 / AD9081 FMC Module

Product Updates

MxFE® Quad, 16-Bit, 12 GSPS RF DAC and Quad, 12-Bit, 4 GSPS RF ADC (AD9081)
MxFE® QUAD, 16-Bit, 12 GSPS RF DAC and DUAL, 12-Bit, 6 GSPS RF ADC (AD9082)

This Vita57.1/ JESD204B/C compliant FMC module is powered by Analog Devices' AD9081 or AD9082 multi-channel ADC/DAC chip and HMC7044 attenuator. The main interface with a host FPGA is supported through 8 serial transceivers.

ADC (AD9081) Parameters

nFlexible reconfigurable radio common platform design
-FDD and TDD single and multiband radios
-Tx/Rx channel bandwidth up to 1.6 GHz/2 GHz (4T4R)
     -Dual use ADC option (receive and transmit DPD) for TDD
-4D4A (4 × 3 GSPS to 12 GSPS DAC and 4 × 1.5 GSPS to
     -4 GSPS ADC)
     -Supports transmitter IQ input data rate up to 1.5 Gbps
     -Supports receiver IQ output data rate up to 2 Gbps
-RF DAC/RF ADC output/input −3 dB bandwidth of 5.2 GHz
    and 7.5 GHz
-On-chip PLL (6 GHz to 12 GHz) with multichip synchronization and
    output clock provided
-External RF clock input option
n AC performance target
-ADC test conditions (3 GSPS, −1 dBFS, fIN < 1.4 GHz)
      -NSD = −149 dBFS/Hz, HD2 < −70 dBc, HD3 < −70 dBc,
          SFDR (excluding HD2, HD3) < −78 dBc; IL < −75 dBc
-DAC test conditions (12 GSPS, −7 dBFS, 2.65 GHz)
      -NSD = −158 dBFS/Hz, SFDR < −74 dBc
n Versatile digital features
-Supports real or complex digital data (8-, 12-, or 16-bit)
-Configurable digital up/down conversion (DDC/DUC)
     -8 fine complex DUCs and 4 coarse complex DUCs
     -8 fine complex DDCs and 4 coarse complex DDCs
     -2 independent NCOs per DUC/DDC
     -Option to bypass fine and course DUC/DDC
-Programmable 192-tap FIR filter
nReceiver AGC support
-Fast detect with low latency for fast AGC control
-Signal monitor for slow AGC control
-Dedicated AGC support pins
-Transmitter DPD support
-Fine DUC channel gain control and delay adjust
-Coarse DDC delay adjust for ADC observation path
n Auxiliary features
-Fast frequency hopping
-Low latency digital loopback mode (ADC to DAC)
-ADC clock driver with selectable divide ratios
-Power amplifier downstream protection circuitry
-On-chip temperature sensor
-Programmable GPIO pins
-ADC clock driver with selectable divide ratios
-TDD power savings option
nSERDES JESD204B/C Interface, 16 lanes up to 24.75 Gbps
-8 receive lanes for RF DAC
-8 transmit lanes for RF ADC
-JESD204B compatible with the maximum 15.5 Gbps lanerate
-JESD204C compatible with the maximum 24.75 Gbps lanerate
-Sample/bit repeat mode for receive lane rate matching

DAC (AD9082) Parameters

n Flexible reconfigurable radio common platform design
-4D2A (4 × 3 GSPS to 12 GSPS DAC and 2 × 3 GSPS to 6 GSPS ADC)
-4D1A (4 × 3 GSPS to 12 GSPS DAC and 1 × 3 GSPS to 6 GSPS ADC)
-RF DAC/RF ADC output/input −3 dB bandwidth of 5.2 GHz and 7.5 GHz
-Transmit/receive channel bandwidth up to 1.6 GHz/3 GHz (4T2R)
-Transmit/receive channel bandwidth up to 2.4 GHz/3 GHz (2T2R)
-On-chip PLL (6 GHz to 12 GHz) with multichip synchronization; output
   clock provided
-External RFCLK input option
n AC performance target
-ADC test conditions (6 GSPS, −1 dBFS, fIN < 1.4 GHz)
    -NSD = −154 dBFS/Hz; HD2 < −70 dBc; HD3 < −70 dBc; SFDR
   (excluding HD2, HD3) <−78 dBc; IL < −75 dBc
-DAC Test conditions (6 GSPS, −7 dBFS, 1.8 GHz)
    -NSD = −158 dBFS/Hz; SFDR < −74 dBc
nVersatile Digital Features
-Supports real or complex digital data (8-, 12, or 16-bit)
-Configurable DDC/DUC
    -8 fine complex DUCs and 4 coarse complex DUCs
    -8 fine complex DDCs and 4 coarse complex DDCs
    -2 independent NCOs per DUC/DDC
    -Option to bypass fine and coarse DUC/DDC
-Programmable 192-tap FIR filter
nRxAGC Support
-Fast Detect with low latency for fast AGC control
-Signal Monitor for slow AGC control
-Dedicated AGC support pins
nTransmit DPD support
-Fine DUC channel gain control and delay adjust
-Coarse DDC delay adjust for ADC observation path
nAuxiliary Features
-Fast frequency hopping
-Low latency Digital Loopback Mode (ADC to DAC)
-ADC clock driver with selectable divide ratios
-PA downstream protection circuitry
-On-chip Temp Sensor
-Flexible GPIO pins
-ADC clock driver with selectable divide ratios
-Power amplifier downstream protection circuitry
-On-chip temperature sensor
-Programmable GPIO pins
-TDD power savings option
nSERDES JESD204B/C interface, 16 lanes up to 24.75 Gbps
-8 receive lanes for RF DAC
-8 transmit lanes for RF AD
-204B compatible with the maximum 15.5 Gbps lane rate
-204C compatible with the max 24.75Gbps lane rate
-204C compatible with the maximum 24.75 Gbps lane rate
-Sample/bit repeat mode for receive lane rate matching

Features

► Vita57.1 FMC HPC Connector
► x1 AD9081 or AD9082
► SSMC RF Connectors
► External ADC Clock

Ordering information

- Part Numbers:
HTG-FMC-AD9082
HTG-FMC-AD9081

- Price: Please contact us

12" SSMC To SMA Cable
24" SSMC To SMA Cable

ECCN #: EAR99
SCHEDULE B #: 8471601050

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